286 was an RTL model hand converted module by module to transistor/gate level schematic. Afair 386 was the first Intel CPU where they fully used synthesis (work out of UC Berkeley
https://vcresearch.berkeley.edu/faculty/alberto-sangiovanni-... co-founder of a little company called Cadence) instead of manual routing. Everything went thru logic optimizers (multi-level logic synthesis) and will most likely be unrecognizable.
I found a paper on this 'Coping with the Complexity of Microprocessor Design at Intel – A CAD History'
https://www.researchgate.net/profile/Avinoam-Kolodny/publica...
>In the 80286 design, the blocks of RTL were manually
translated into the schematic design of gates and transistors
which were manually entered in the schematic capture
system which generated netlists of the design.
>Albert proposed to support
the research at U.C. Berkeley, introduce the use of
multi-level logic synthesis and automatic layout for the
control logic of the 386, and to set up an internal group to
implement the plan, albeit Alberto pointed out that
multi-level synthesis had not been released even internally to other research groups in U.C. Berkeley.
>Only the I/O
ring, the data and address path, the microcode array and three
large PLAs were not taken through the synthesis tool chain
on the 386. While there were many early skeptics, the results
spoke for themselves.
With layout of standard cell blocks automatically
generated, the layout and circuit designers could myopically
focus on the highly optimized blocks like the datapath and
I/O ring where their creativity could yield much greater
impact
>486 design:
A fully automated translation from RTL to layout (we called it RLS: RTL to Layout Synthesis)
No manual schematic design (direct synthesis of gate-level netlists from RTL, without graphical schematics of the circuits)
Multi-level logic synthesis for the control functions
Automated gate sizing and optimization
Inclusion of parasitic elements estimation
Full chip layout and floor planning tools