ASML looking to finally get ahead of Moore’s Law
bits-chips.nl
bits-chips.nl
They reportedly can’t meet demand and the current backlog for new machines is at 2+ years. Surely a company in a sector with such massive capital expenditures has better use of this money? For example scaling production or R&D?
Specifically my guess (and I'm no expert) is a plasma wakefield accelerator feeding a free electron laser to get tunable wavelength EUV light far cheaper and simpler than what they've got now. Tons of work to do to get there, but that's always been the case in thier business. Also, if they don't do it someone else might and then they'd be dead.
There are other R&D areas to be handled too. One might ask why not spend more on the R&D, but they are probably at some kind of practical limit there too.
Don't you think they'll also be using a retro encabulator, with the modial interaction of magneto-reluctance and capacitive directance being used to generate the EUV light?
(I've also just realized at least 10 companies have probably re-shot this internally with their own equipment. Argh.)
Wish I could upvote tenfold to further increase your customer focus on operator excellence.
You can use a big accelerator as a EUV light source. The SLAC beamline was once used to test the concept. Medium sized (160m circumference) synchrotrons have been suggested.[2] One appears to be under construction in China.
A plasma wakefield accelerator is a proposed way to shrink a powerful accelerator down to a more manageable size. Maybe. There's a project underway to use about a third of the 2-mile long SLAC beamline in this mode.
ASML made zapping a droplet of molten tin with lasers work as an EUV source. That's a nightmare. This approach may or may not be better. It involves zapping a high-pressure gas with lasers.
All the known ways to do this are insanely expensive and look more like physics experiments than production equipment.
A clean light source, where you put electricity in and get EUV out, would be easier to work with. There was talk of "table top synchrotrons" a few years back. One startup built one, although it was more like garage-sized.
[1] https://www.cambridge.org/core/journals/high-power-laser-sci...
[2] https://pubmed.ncbi.nlm.nih.gov/35228673/
[3] https://www6.slac.stanford.edu/news/2020-10-12-slac-starts-n...
Can recommend [1] as the title say about the light source. Very interesting even for a non professional (and [2] as on high level overview of the machine and [3] as longer documentation inside ASML).
[1] https://www.youtube.com/watch?v=5Ge2RcvDlgw "The Extreme Engineering of ASML’s EUV Light Source"
[2] https://www.youtube.com/watch?v=f0gMdGrVteI "The Extreme Physics Pushing Moore’s Law to the Next Level"
[3] https://www.youtube.com/watch?v=zQu_TMgHO98 "ASML's Secret: An exclusive view from inside the global semiconductor giant"
Is this named after the town, a person, or just 'wake' and 'field'?
Please be the town. If Wakefield can get in on the plasma accelerator sexyness, there's hope for all boring northern towns.
Dewsbury fusion here we come.
https://en.wikipedia.org/wiki/Plasma_acceleration#Wakefield_...
In the Netherlands, appreciation is immediately taxable for individuals, but not for corporations.
I presume you don't send a cheque off for €1.36 at the end of the day, (or receive a cheque back after 8 months)
Of course this state of affairs relies on companies not all jumping to stock buybacks, or else the treasury will find some new way of getting their pound of flesh
Stock buybacks manipulate the stock price. That's not an equivalent purpose. It even used to be illegal.
Nobody else can get the job done. So, as they say, it is what it is.
https://en.m.wikipedia.org/wiki/Carl_Zeiss_SMT
15 years ago, when I was there, Zeiss SMT also did the light sources (discussed elsewhere in the thread), btw, not just supplying the lenses. Don't know if that's still the case. I don't know exactly what the lens/mirror systems for EUV look like, but the "old" 193nm ones were something to behold.
The annual report states that they don't grant stock options since 2017 and there is no word about stock based compensation in the balance sheet.
So, it's really hard to scale that process for building new machines.
They've got money burning in their pockets and no better place to spend it, so what do they do? Stock buybacks.
Disclaimer: I did a six month contract working for them several years ago, when they were towards the start of developing their EUV process. It was a real eye opener to have the tour of the facility and have everything explained to me.
Veldhoven :)
I agree with you that the need maybe will not be there exactly when they have built out.
Also note that TSMC, Intel and a whole bunch of others are currently starting to build, or plan to build, new fabs (partly due to the new Chip Act). And they will need stuff from ASML.
https://www.youtube.com/watch?v=TL9Q435KU_Y
I don't think they are "completely disassembled" before shipping.
My point is that the size of the container tells something about the size of the components. "Completely disassembled" would mean every nut and bolt would be taken apart, which I don't think is the case given the size of the container.
And you're missing the fact that the outside of the box isn't a clean room, and it has to mate with the clean room at the customer facilities. A bajillion baggies of parts is a non starter if the outside of those baggies isn't a clean room env.
>Peter Wennink made €4,820,000 in total compensation as Co-President, Chief Executive Officer and Chairman of the Board of Management at ASML Holding in 2021. €1,020,000 was received as Total Cash, €3,537,000 was received as Equity and €263,000 was received as Pension and other forms of compensation.
The term for this is a positive feedback loop.
>Positive feedback in amplifier If the feedback signal is in the phase with the input signal, the effective input to the circuit is increased and this type of feedback is called positive, regenerative or direct feedback. It provides increased gain but it also increases distortion and leads to poor stability of gain.
I asked TinEye [1] where I can get that stock photo. It turns out you can get it at most of the big stock photo sites. For example, here it is on Shutterstock: https://www.shutterstock.com/image-photo/software-source-cod...
If I was a junior programmer considering to apply at ASML this picture would give me “ok these folks don’t understand software” vibes.
ASML is not one of these companies.
I assume both depts in any company don't understand payroll, I don't think that would give anyone cause for concern about actually getting paid.
There's a reason why people specialise. The fact that one dept doesn't understand the work of another dept isn't a surprise.
Surely there will be an inevitable insurmountable plateau reducing cost and performance gains to smaller improvements.
At some point, different technologies will have to be seriously considered such as photonics.
Edit: here is the clip https://youtu.be/c01BlUDIlK4
Another option would be to not go 100x faster but to go 10x faster and then take the improved cooling + energy usage as a win.
It will be true some day, and maybe that's now, but I've stopped thinking we'll know before it happens.
I seem to remember this was an argument made with Josephson Junctions back in the day. They were potentially better, but always far enough out that traditional technologies would exceed the projected performance by the time they launched.
So maybe we need to hope for current trends to plateau if we want something new to replace it.
TIL that NA stands for numerical aperture, which is a measure of how much light the optical system can collect and focus.
The silicon atoms do not behave like spheres, only the atoms from many metallic or ionic substances have a behavior close to that of spheres. So it makes no sense to speak about a length "across" a silicon atom.
In the case of silicon, a meaningful number is that there are around 50 silicon atoms per cubic nanometer of silicon crystal.
The gate of a transistor (which is the active part of the transistor, and which has a much smaller volume than the complete transistor) in the latest 5-nm technologies is contained in a fin that might have a width around 5 nm, a length around 20 nm and a height around 50 nm, for a volume around 5000 cubic namometers (it is a complete coincidence that the width of a fin might be around 5 nm to 6 nm for a process named as "5 nm"; there is no relationship between the name of the process and the width of the fin; fins did not even exist for processes with names greater than "22 nm"). Such a gate of the smallest transistor might include around 250 thousand Si atoms. The volume of the complete transistor would be at least 10 to 20 times greater.
However the size of a transistor is not limited by the number of silicon atoms in the gate, but by the number of impurity atoms that control the conductivity of the silicon, and those are much less than the silicon atoms (I have not seen any number for the latest technologies, but they could be e.g. 10 thousand times less than the silicon atoms, so there might be less than 100 impurity atoms in the gate).
Could you expand a bit? If atoms were randomly arranged, or in a non solid state I could kind of understand. But once you get to any kind of fixed structure you can infer 2d spacing from 3d spacing.
Or is your intent to say that the quantity of silicon in a gate is 3d, especially with fins, so a 2d view doesn't give a complete picture?
Because of that, the atoms are not packed together like some spheres, i.e. like the atoms in metallic aluminum or in table salt, where you may speak about the diameter of the atomic spheres. They are distributed on a lattice that has empty spaces between atoms and their bonds (i.e. the places where electrons belonging to the atoms are located with high probability).
The distance between the silicon atoms in a silicon crystal varies depending on the direction, so there is no single value that could be considered the diameter of a silicon atom.
The periodic cell of a silicon crystal has the same structure as that of cubic diamond and it has the form of a cube with 8 atoms inside it (an atom in a cube corner counts as 1/8 inside, an atom on a face counts as 1/2 inside).
A visualization from Wikipedia:
https://en.wikipedia.org/wiki/Diamond_cubic#/media/File:Diam...
While this visualization uses balls and sticks, to show the positions of the centers of the atoms, that has nothing to do with the form of the real atoms.
At most you could consider that a silicon atom has the form of the corresponding Voronoi polyhedron, in which case you would have to give several numbers, to describe its size, and not a single "across" value:
https://en.wikipedia.org/wiki/Triakis_truncated_tetrahedron
The number that I have provided, i.e. 50 Si atoms per cubic nanometer of Si crystal, can be computed by dividing 8 atoms to the volume of the cubic cell of the Si lattice. Given a volume of Si crystal, you can compute the number of Si atoms.
Like I have said, I do not know what means that 0.2 nm value, as the distance between 2 neighbor Si atoms can be larger than 0.5 nm, depending on the direction. In any case you cannot use it to compute anything about the number of atoms in a silicon device.
EDIT: I believe that you might have got your 0.2 nm from truncating the distance between 2 silicon atomic planes in the so-called "111" direction (the direction of the cube diagonal), which is the minimum distance between atomic planes in silicon.
That distance is 0.543 nm * sqrt(3) / 4 = 0.235 nm.
Because this distance is correct only for the "111" crystalographic direction, it cannot be used to compute the number of atoms in some piece of silicon, and it certainly cannot be called as the diameter of a silicon atom ("across an atom" without specifying the direction).
The result is that a 2nm process transistors is on the order of 10s of millions of atoms.
Source: I work with the latest nodes.
Here's a Fermi estimate: the M1 is ~16 billion transistors; assume it is 1 cm^2. That gives (10^7)^2 nm^2 / 10^10 transistors, which is ~10^4 nm^2/transistor. Assume the transistor is ~50nm high, which gives ~5x10^5 nm^3/transistor. There are ~100 SI atoms/nm^3, which gives a volume of ~5x10^7 SI/transistor.
This is not easy business, but there is space for at least one more player.
Remembers me madness on plastic windows in Ukraine, where lot of people buy machine-tools, with dreams, to sell plastic windows forever. Some even build full size factories.
But unfortunately all these ended, because hundreds of small businesses in ~10 years, filled all current needs of people, and plastic windows last about 20 years, so once market shrink by about 95%, because now all these tools will do 1/20 of market per year.
PS sure, war will change things, but even most pessimistic opinions, about 30% of homes need big repair (really much less, but now impossible to know exactly), and with existing capacity, they will be filled in cup of years.
DDR3 was the peak of RAM latency, 65nm SSDs where the peak of flash memory longevity both in ~2010!
You cannot scale anything unless it's embarrasingly parallelizable in which case you never had a problem in the first place.
Peak performance is more important than the puny 0.5Gflops/W "5"nm M1 (2.5Gflops/W) has over the 28nm Raspberry 4 (2 Gflops/W).
Everything that is below one order of magnitude improvement is irrelevant = ASML is irrelevant unless devices break and you buy things you cannot repair.
That combined with eternally raising electricity cost, not as a function of marginal prices on a market (like today), but as a permanent depletion of resources leads to only 1 conclusion:
Don't wait for the next generation hardware/firmware locked, rentseeking line of hardware: 14nm X86 and 28nm ARM IS good enough for a lifetime if you control it and make sure it lasts.
There are only 2 programming languages that can survive this long term: C on the client (with a little ++ for convenience) and vanilla JavaSE on the server (with as little deps. as possible).
Bonus prediction: JavaME will be revived in some form for open microcontroller mobile use.
That’s kind of a big claim, why only these 2?
Those numbers are very misleading - perf per watt is not a constant but something that very much depends on how far the clock speed is pushed. Anything tuned for perf is going to have significantly worse perf per watt than the architecture is capable of. The same goes for the CPU design - maximizing perf and maximizing perf per watt is going to give you different architectures on the same node.
Sheesh, calm down...