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RISC has nothing to do with instruction counts. Think of it as a "set of reduced instructions", not a "reduced set of instructions". It's the fact that every instruction only does something "simple" which you can directly implement in hardware that matters here.

In case it's still not obvious: PowerPC is obviously a RISC ISA, but it has just as many instructions as some CISC ISAs out there. Meanwhile PDP-8 has 8 instructions, but it's clearly a CISC ISA.

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I think "do something simple" is going to get phased out and replaced by "do something useful" over time.

Consider if you want to load a 64-bit immediate into a register under the current RISC-V spec. Takes so many instructions that it's easier to just load a constant from memory, despite memory access being much slower.

    lui r1, 0x01234
    lui r2, 0x89ABC
    addi r1, 0x567
    addi r2, 0xDEF
    shl r1, 32
    or r1, r2

24-bytes, 6 instruction cycles and 2 registers.

In x86_64:

    movabs rax, 0x0123456789ABCDEF

11-bytes, 1 instruction cycle, 1 register.

How many uOps is that instruction in x86_64?

Note that while the performance effect of L1I cache misses is negligible, the complex x86-64 decoder may not be. Some SPECpu2017 have front-end problems due to the x86-64 decoder.

`MOV Rq, Iq` takes one uop with a throughput of up to four(!) per cycle on some ISAs: https://uops.info/html-instr/MOV_R64_I64.html

That's only for a fully general 64-bit value though. Most constants in practical use can be loaded/recomputed a lot more easily.

Practical use is double-precision floating-point constants, preprocessor generated bit-flags, high-bits pointer tagging in dynamic languages, etc. Having to read them from memory or expend multiple cycles to materialize them into a register defeats the point on even having them constant.

This is a red herring and considering that RISC-V binaries are generally the same size or smaller than x86, there are certainly code sequences where RISC-V is much smaller for the same code.

Another interesting metric is that x86 average instruction length is 4.25 bytes[0] which further implies that x86 instructions are only getting longer as time goes by. Meanwhile, RISC-V should continue to get more dense as new instructions are added.

[0] https://aakshintala.com/papers/instrpop-systor19.pdf

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