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Comment by dreamcompiler | Hacker News Reader

And I plan to date supermodels. /s

Okay I'll try to be constructive. TSMC is two things: The biggest contracting foundry in the world, and a leader in EUV application for tiny geometries. I think it's possible for Intel to become a contracting foundry; it goes against their DNA but Gelsinger very much wants to do it. So that's the first thing. Maybe it'll happen.

The second thing is much more problematic.

> Intel is still working on getting its 5-nm mass production going, and says it will begin manufacturing Intel 3 -- its answer to TSMC's 3-nm tech -- in the second half of 2023.

This I'm much more skeptical about. Intel tried to make EUV work before and failed. Still they seem to be buying ASML equipment and installing it at Ronler Acres:

https://www.protocol.com/enterprise/intel-euv-fab-chips

But it still sounds like a long shot to get it working in 2023.

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Some other things I noticed when I read their earnings call transcript from the other day:

"We'll start with a focus on driving $3 billion of cost reduction in 2023, 1/3 in cost of sales and 2/3 in operating expenses."

"best-in-class semiconductor companies have a financial profile that includes gross margins in the 60s" (Intel's is in the mid 40's and fell last quarter)

So they're not only trying to change a gigantic part of their business model, but ALSO drive $3B of cost reduction and try and push gross margins back up to... where they were 5 years or so ago?

They're making it impossible for themselves IMO. Pivot or profit improvements, choose one. Doing both at the same time is surely going to lead to a huge mess.

The thing to understand about Intel is that the finance org has hugely outsized power compared to other companies. This is a company that believes that any problem can be solved with capital allocation, and no project is worth doing unless there’s a financial analysis “proving” it will add at least $1B/year to the bottom line.

Intel’s culture is that of a cash cow, not an innovator. So year, profit improvements come naturally, pivoting not so much.

I worked with IBM in the early 2000s porting some IP to their processes and what was so difficult was that everything was proprietary to IBM. From the nomenclature, to the tools, to the models, etc. That was great when they were on top, but the world passed them by and there was no hope of converting them over. I never worked with Intel the same way, but some close friends did and it sounds exactly the same. They are proprietary and very inefficient. A block that would normally be laid out in two days, Intel would spend two weeks on. Their process design rules were super restrictive and their tooling just isn't efficient compared to the what the rest of the industry now uses. Unique, strict and obnoxious design rules might be OK when you are designing a high-volume processor like Intel, but that is not the kind of process you want for a foundry.

I fear it is not in Intel's DNA to make this switch.

Would you share some insight on why Intel failed at making EUV work? Gelsinger said on a podcast (Decoder) recently that in fact they fought it.

Obviously, they are kind of big enough to do both — make a half hearted attempt and fight it all the same due to some internal politics. However, for something this existential, one would think that the smart people and the leadership would try to put some focus on the field. Was it that bad? Really, looking for some insight on what really went down.

Intel (like every other chipmaker) has been chasing EUV for decades, but every time they thought they finally nailed it they turned out to be wrong.

The key that ultimately made it possible was the light source, and ASML is the only company that sells these light sources. ASML didn't invent the light source entirely on its own; there were a lot of ideas for light sources floating around and the only one that turned out to work was laser-induced plasma from tin microdroplets, which sounds completely crazy but it works [0]. ASML perfected that process (with -- to be fair -- some investment from Intel).

[0] https://www.asml.com/en/technology/lithography-principles/li...

Intel did fight EUV with a technology called SAQP which ultimately turned out not to work as well as EUV, but they were researching EUV at the same time. Here are some more historical articles about Intel's work on EUV in the past. Note the dates.

https://newsroom.intel.com/news-releases/intel-achieves-majo...

https://semiengineering.com/why-euv-is-so-difficult/

https://www.eetimes.com/intel-developing-euv-pellicle/

https://www.extremetech.com/computing/276376-intel-reportedl...

Thank you.

Do you have any insight on what organizational failures led to them failing to find the right EUV solution?

Was it just a matter of luck that ASML nailed the right one or was it the nature of exploring some riskier alternative (as you said "which sounds completely crazy but it works")?

I know nothing about Intel's internal organization.

There were several different light source ideas tried. Some at US national laboratories. Tin plasma was known to work but it left so much debris that it gummed up the optics so it was forgotten for a while. The key turned out to be tin microdroplets.

https://www.optica-opn.org/home/articles/volume_29/march_201...

ASML and Intel are two completely different companies. ASML makes lithography machines which is one of the many steps in producing a chip. ASML machines are used by all chip manufacturers. The challenge for chip manufacturers like Intel, but also tsmc, Samsung among others, is to optimize the entire production process. And that has been / is not easy with a lithography step (EUV) which is so drastically different then what the industry has been using before. One of the challenging choices for chip manufacturers was to drastically change the process and implement EUV or to go self-aligned quadratic patterning. The latter, if you take a simplistic view, can be seen as an evolution on existing processes. We know see that those companies who went aggressively into EUV are having an edge on their competitors.

When they say “microdroplets” (I may be out of date here) they mean firing lasers at falling drops of molten tin and then capturing the energy that the tin gives off.

Like anything, some of their PHDs were like “no that’s probably not going to work because xyz” and they trusted said PHDs.

It’s just science. It’s hard to predict.

I think it's more that they didn't try ('till now) 'cause they thought ASML's machines just weren't ready for prime time. TSMC bought ASML's bleeding edge EUV machines thinking they could make it work eventually, and they did. Intel may catch up very quickly now.

I thought that ASML got its EUV light source, basically, by buying Cymer in San Diego. Read some of [0], and then searched it, but didn't find a single instance of 'Cymer.'

I am much more hopeful about Intel's chance at EUV than GP. In order to avoid repeating myself, here's my analysis of what went wrong: https://news.ycombinator.com/item?id=32335873

Why is it that it's taking them so long to pivoting from that failure? 10nm didn't work out, that's fine. But it feels like that didn't work out and they've spent the years after that in a hole and still haven't dug themselves out.

From the rumors I've heard (might be true; might not) Intel lost a great deal of semiconductor engineering talent because they were making so much money on minor evolutions of x86 that they saw little need to truly innovate. The MBAs took over.

Once it became clear that AMD and ARM (and by extension TSMC) were eating their lunch, they had great difficulty pivoting because they lacked the talent and the organizational will to do so -- at least until Gelsinger took charge. I have a lot of respect for Gelsinger and I think he just might turn it around.

> ...they were making so much money on minor evolutions of x86 that they saw little need to truly innovate. The MBAs took over.

Yet another example in a long history that modeling your talent pipeline as a JIT supply chain does not work in high cognitive input settings. This is a general unsolved management challenge: capturing sufficiently granular and comprehensive institutional knowledge to be able to efficiently restart organizations that rely upon it years down the line.

I don't think we will ever solve it until we learn how to share human mind states. The complexity of these high cognitive input activities at large scale has surpassed the ability of our capabilities to transfer comprehension between minds using conventional information transfer techniques (primarily written word and audio video). Even were I to guarantee the capture of all information at sufficient granularity, the only way to QA that is to de novo staff up a brand-new parallel organization, and have them reproduce the original organization's accomplishments. No one is ever funded for that.

This is a really interesting problem space for me because I suspect it is a dimension of technical debt very rarely explored because our species has not had to really grapple with it before as our technological progression has been slow enough we could "good enough" brute force our way through it whenever it came up in less severe forms.

Intel has mastered 10nm production.

The race to the bottom of physics is not a long ride.

> Would you share some insight on why Intel failed at making EUV work? Gelsinger said on a podcast (Decoder) recently that in fact they fought it.

A cursory Google search results in multiple search hits from recent news pieces announcing Intel buying their EUV kits from ASML.

If Intel is handing out small fortunes to ASML to deliver a machine that in the past Intel was expected to develop in-house, that does not sound like a success story.

Here's a Reddit thread on the topic:

https://www.reddit.com/r/AMD_Stock/comments/miar30/why_is_in...

>Intel tried to make EUV work before and failed

Where does it said that? They haven't even launched their first node with EUV yet. So arguably they haven't failed.

I am not entirely sure if Intel needs to overtake TSMC, they just need to be a good enough alternative. But I agree even that is a tall order.

Is it really though? Intels roadmap seems to place them manufacturing on 3nm by 2024 and TSMC is having issues with their 3nm atm, iirc. It seems like competitive advantages in this industry stems from one of the major players getting caught up on a given new node/process.

It depends, it is not yet clear what Intel meant by 3nm in 2024. Shipping hundreds of wafers? Or Real Product launches by their customers?

It is the same with Samsung which arguably ship their 7nm ahead of TSMC. But with low volume, yield and poor performance characteristic it doesn't really matter. ( And I haven't even mentioned cost yet )

They're already using euv. They didn't try to use euv and failed, they tried to stay on duv too long and couldn't get the yield they needed for too long, that was the mistake.

No I plan to rival your dating of the supermodels so you have to date regular models /s

Can you explain what EUV is? I'd prefer an ELI5!

Chips are made by etching lines into a special kind of glass. The etching is done with light. The smaller the light, the smaller the lines. Red light is big, violet light is small. Extreme ultra-violet light is really small, so they can etch really small lines. When the lines are small, the electricity moves through them more quickly, so the chip’s work gets done faster.

When the lines are smaller, you can place more transistors/functionality in the same area, which leads to higher performance. The power required decreases too.

Can you explain how the transistors are placed on the glass? Are they also "etched" by the EUV light?

They are etched and filled with different elements. So a traditional mosfet Transistor needs n, p and gate layers.

They are put on there by putting chemicals on specificatic places. Because it's such a complex pattern, it's easiest to use a template and spray the chemicals on, the same way some artists apply spraypaint.

The template is first printed on the glass. This is done by putting a light sensitive layer (photoresist) on the glass, and exposing some of it to light. When the light gets put on there the properties of the photoresist change so you can wash off the parts you don't want. Jl6 called this process "etching" (there may be additional steps that can also be described as etching, I don't know. Semiconductors are made with a lot of processes. This is the most well known process).

Then you spray on the chemicals you want, and then you wash away the remaining photoresist so you can put the next layer on.

This happens a lot of times for a modern chip.

Additional to what has been posted already, the shape of the lines (which ultimately will result in transistors) is defined by manufactured patterns on quartz glass photomasks[1]. AFAIK a modern processor design has a stack of around 40-60 masks placed in sequence for the light to pass through. Producing these photomasks follows a similar manufacturing process from a lithography POV, except that electron-beams[2] are used instead of a light source. The mask manufacturing process requires its own specialized machines and Intel owns companies that produce those, eg. IMS Nanofabrication[3].

[1]: https://en.wikichip.org/wiki/mask

[2]: https://en.wikipedia.org/wiki/Electron-beam_lithography

[3]: https://www.ims.co.at/en/

The last I heard was TSMC's mask count for 3nm chips is back at just under 100. EULV had brought it down but it's right up there again at the latest node. You really need to avoid those all-layer re-spins!

I looked around at several ELI5-type sources and honestly the Wikipedia one is the best I came across.

https://en.wikipedia.org/wiki/Wafer_fabrication

Here is ASML specifically, in a very slow slideshow format, representing our finest web technology.

https://www.asml.com/en/technology/all-about-microchips/how-...

So technically, we could use Xrays/Gamma rays to get even smaller.

If you had the requisite optics, perhaps.

https://en.wikipedia.org/wiki/X-ray_optics

So essentially, these chips are made by shining the design through a mask over a silicon disc coated with photoactive chemicals and then chemically processed to make that design "stick" depending on what parts were illuminated and what parts were not, much like old school photography. There's no physical etching going on, its a chemical process where light is used to "activate" certain parts of a coating.

The wavelength, or the color of the light here limits how much minified image we can shine and currently the Extreme ultraviolet lithography(EUV) is the state of the art where they use ultraviolet light with 13.5nm wavelength. As different materials behave differently under different light wavelengths, EUV requires different process to shine the mask over the silicon disk. One major difference from the previous processes is that in EUV lithography they use mirrors instead of lenses to direct the light.

So far, it's only the European manufacturer ASML who managed to perfect this process for mass production.

I don't think they really have a choice but to do this. China is moving hard for Taiwan, and they are serious.

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