What's different about next-gen transistors
semiengineering.com
semiengineering.com
^---^
( 'o' )
( u u )And yet today, nothing came out of it. Sure, you can still buy FeRAM at digikey, and it found a niche or two by itself, but it is tiny, tiny piece of overall storage market.
I think that memristor is going to end up as FRAM and not as MEMS. It is cute, but even if it could be executed perfectly, it does not allow anything that more conventional technologies can do (unlike MEMS :) l
Memristors are a specific electric component.
https://en.wikipedia.org/wiki/Microelectromechanical_systems
https://en.wikipedia.org/wiki/Memristor
While MEMS is already huge and still getting way bigger, memristors ain't really a thing yet.
https://semiengineering.com/entities/asml/
https://en.wikipedia.org/wiki/ASM_International
https://www.asml.com/en/company/about-asml/history
From the last one, ca. 1988 ASML was failing badly:
"But in a market of fierce competition and many suppliers, the small unknown company from the Netherlands couldn’t catch a break. ASML had few customers and was unable to stand on its own two feet. Making matters worse, shareholder ASMI was unable to maintain the high levels of investment with little return and decided to withdraw, while the global electronics industry took a turn for the worse, and Philips announced a vast cost-cutting program. The life of our young cash-devouring lithography company hung in the balance. Guided by a strong belief in the ongoing R&D and in desperate need of funds, ASML executives reached out to Philips board member Henk Bodt, who persuaded his colleagues to lend a final helping hand."
(I understand that nowadays you need their equipment for new fabs.)
A lot less critical, I've read that Olivetti vanished from the industry due to random finance wars between France and Belgium with some bank (which bought the company not long before) crashing and thus cutting money right at the moment where PC were taking off.
So how are the multiple layers done, if light is shined on the surface, how do you reach the other layers? And how is this doping done, you also need to choose what element goes where but this couldn't be done with light and a mask I'd think (so even if single layer I wonder how this works)? And how do you reach the other layers with those chemical elements for doping?
And I believe there were steps to flatten and I believe effectively sand the surface flat after some layers.
Would note that since FinFETs, deposition occurs from the side as well as top.
The Wikipedia article on CMOS has a very nice illustration of the basic steps of this process: https://en.wikipedia.org/wiki/CMOS#/media/File:CMOS_fabricat... Current processes are much more complex than even that.
For step 7 for example, you create a masking layer that way, after which you etch away only the exposed parts where source and drain contacts will end up.
For step 8, you do something similar. The openings you’ve etched in step 8 will allow only to dope the contacts, but you need to mask the nmos and pmos separately, otherwise you get the same doping in both transistors.
A lot of the ‘magic’ to make this work is in the materials and chemistry: you need selectivity: etching that only interacts with the exposed parts. In highly scaled finfet nodes, the material combinations are very complex as you sometimes want 2, or 3 different material combinations to interact in the way you want, reliably, at nanometer scale.
(Edit finfet not finger)
For each layer of metal, they go through several steps of deposition of insulator, masking, etching, deposition of metal (often in several passes now), grinding or etching that, and then covering it all up with more insulator and grinding that layer down to produce a smooth surface for the next layer.
Once the chips are complete, 3D stacking is a packaging process. It involves grinding the backsides of the chips down until they are very thin and attaching the dies together using vias that run through the thin remaining silicon layer.
EDIT: Flash memory today has multiple stacked doped silicon layers, but it is a special process that is largely unsuitable for logic.
Or has the space already been explored and there's nothing there?
What I was trying to say is that there are things we don't do because they're hard or we don't know how, and there are things that we don't do because we've proven they don't work.
Ternary does have some cool features though.
For digital, noise-free logic, it's generally more power efficient and physically simpler to have logic gates operate on two cleanly separated states with more gates, than to have bulkier, more complicated gates that do the same thing with combined states. A transistor which is fully on or fully off in a logic circuit uses low power either way (like a wire or a gap in the circuit), but the in-between state uses more power (like a resistor, it produces heat). This is one reason why power consumption goes up with the amount of logic state switching (the in-between resistor-like state occurs briefly during each state change), and also why many-level stable logic states aren't so efficient, except with complicated gates that use many transistors to implement many thresholds.
For non-volatile storage, that doesn't apply. Information density is more important, individual memory cells do not change state often so switching power is less of a thing per memory cell, and the logic sits at the edge of the memory array, shared among many cells. The edge circuitry can afford to be more complicated, to optimise the bulk of the memory array.
In magnetic storage and communication, the signal processing to encode many states in a small signal takes considerable power, but the trade off is worth it.
I checked Mouser just now and memristors are not in stock: https://www.mouser.com/c/?q=memristor
If we are talking about imaginary components, then I think quantistors will change everything.
If you are interested in learning, the idea of memristors (and other computational memory technology) is not to replace traditional memory, but rather to augment small portions of it with increased/additional computational functionality.
For example, you could add a (relatively speaking) extremely small number of memristors to an existing memory module, load two matrices into that area of memory, and reading from the adjacent region of memory would immediately yield the result of multiplying those two matrices. If you could simply instruct the RAM module where the existing data lies, this would be an immense boost in efficiency to AI/deep learning prediction algorithms. Here is a video explanation of how this could be use to perform matrix vector multiplication in O(1): https://youtu.be/30K5i8bdiyg?t=1492 .
That video mentions later that something similar can be used in solving linear and partial differential equations. Applications for deep learning training is discussed at 40:20 .
You'll notice everything discussed in the keynote has experimental results. At 41:27, he mentions that you can actually send images to their memristor chip over their website . Though the link is unfortunately dead, it definitely worked, and was in fact performing neural network computations using memristors over the network.
Without the buffering step, you'll eventually get the middle logic levels drifting (e.g. your "1"s become "0"s or "2"s). Binary gets this for "free" because there's no middle states; this doesn't apply just to a simple buffer, similar details apply to the implementation of all other gates (many of which are rather awkward to implement).
Analog works out for rough calculations because you can skip the buffering process, at the expense of having your calculation's precision limited by the linearity of your circuit.
SSDs are more of a special case, because to my knowledge they're not really doing work on multi-level logic outside of the storage cells. They pump current in on one axis of a matrix, read it out on the other, and then ADC it back to binary as fast as possible before doing any other logic.
Random sidebar: I don't see any constraint like this for mechanical computers, so a base-10 mechanical computer doesn't strike me as any more unreasonable than a base-2 mechanical computer (i.e. slop and tolerance is independent of gear size). In fact, it might be reasonable to say you should use the largest gears that the technology of your time can support (sorry Babbage).
Whatever the future holds, it’s clear that the industry is in no hurry to abandon silicon, despite the theoretical advantages of alternative materials. “””
Such as? What a frustrating way to leave us dangling.
Impressive.