I am too lazy to search right now through the library, but there are plenty of books about the history of electronic computers, which describe some of the vacuum-tube computers of the fifties which introduced various innovations, e.g. the computers built by NBS (SEAC & SWAC), various IAS derivatives, the IBM scientific computing series starting with IBM 701, and many others. For some of the early computers there are manuals at bitsavers.org.
All the early computers had by necessity features with low implementation cost, i.e. hardwired control, fixed-size instructions, simple addressing modes, low number of instructions, etc.
The RISC CPUs returned to this simplicity, but they did not become completely similar with the early computers because the early computers did not have a large set of registers allowing the computations to be done by register-register operations.
The early computers did not have many registers for 2 reasons, first they would have been too expensive when made with discrete components, and second there was no need for them because the memory access was fast in comparison with the instruction execution time.
Nevertheless, the concept of an ISA separated in register-register computational instructions and load/store instructions for accessing the memory has also not been newly introduced by the RISC projects, but it dates back to the CDC 6600, in 1964, even if at that time having only 8 data registers was the reasonable register set size.
So all the RISC recommendations had been used, for various reasons, in earlier computers.
What was new with RISC, and this has appeared for the first time in the IBM 801 documentation, i.e. in 1975/1976, was the idea that by returning to the original simplicity of the older computers less hardware resources are needed to implement the CPU, and then the saved hardware resources can be used to implement other features that have a higher impact on performance, e.g. a larger register set, on-chip cache memory, faster parallel multipliers, and so on.
The RISC approach was a more rational CPU design optimization methodology, which advocated the measurement of the complete performance impact of any new feature, e.g. an extra instruction or addressing mode added to the ISA, and the rejection of the features which add too much cost while providing too little performance increase or even a performance decrease, because the added feature might accelerate a seldom used application, while slowing down all the frequently used applications.
The optimization approach proposed by RISC remains as correct today as in 1975 or 1980, but when different manufacturing technologies are available the optimum CPU design can be very different.
While including certain instructions in the ISA might have been a bad choice in 1980, e.g. an extra instruction for computing the tensor product of 2 vectors, a performance vs. cost analysis done in 2020 might conclude that it is in fact the best change that could be done to an ISA in the given technology, in order to provide maximum additional performance at minimum additional cost.
So what must be retained from RISC is not e.g. the necessity of having a fixed-length instruction encoding, or any other feature that was optimal in 1980, and which might happen to be still optimal in 2022, but this is not certain and it must be demonstrated by a new analysis, based on the current technological capabilities.
What must be retained from RISC is that CPU design is an optimization problem and any features of a design must be justified by concrete performance and cost numbers, and not by vague ideas about what might be useful or not useful to have in a CPU.
What is frustrating when looking at modern CPU or GPU designs, e.g. Zen 4, Raptor Lake or the RTX 4000 series, is that an outside observer cannot really assess whether the CPU or GPU design teams have done a good job or not.
An outside observer can measure the performance, i.e. the speed and energy consumption of a CPU or GPU when performing certain tasks, but there is no access to the cost information, which is a closely guarded secret, because foundries like TSMC do not provide design rules information, unless you are a potential big customer.
So an outsider cannot judge whether the current CPU and GPU architectures and micro-architectures are the best that can be done, or significant improvements are possible.