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Comment by dtx1 | Hacker News Reader

Can someone estimate the power of these new FPGAs? Is a MisterFPGA with n64/PS2 emulation in range?

Yes, but that's not the problem. The problem is these Agilex devices are insane overkill for that task, and you likely won't be able to buy the SKUs in a reasonable form factor or price for that use case. The Mister worked so well because the actual design of the device has the right blend of peripherals/compute and Intel/terASIC ate the NRE to design and manufacture it, and that's because they intended it use it to teach and educate people and needed a lot of volume for that. Agilex isn't a teaching part. It's their most advanced top-of-the-line part with its own logic design requirements that differentiate it from earlier lines (Arria 10 and prior.)

You likely aren't going to see "consumer-oriented" Agilex-powered devices in similar form factors anytime soon; most of the compute power of the fabric would be completely wasted without fast peripherals/storage anyway (the fabric can be clocked very high if you pipeline enough) and the shipping volume to make the boards attractive/low-price enough would need to be pretty decent. This means the board would actually end up expensive; why pay so much for the FPGA if all the I/O sucks? But good I/O is expensive. The Agilex parts are some of Intel's most complex devices on their latest "Intel 7" process too, it's not cheap.

I guess it's maybe something that would be possible to crowdfund in low volumes, but it's a truly huge amount of work even before you get to price. Designing the board, getting the software and tools working, documentation, that's before you even manufacture. And realistically there are probably other FPGA options that would be cheaper and more readily available. Something like a Kintex-7, or Arria 10 part would probably do just as well for significantly cheaper, I'd think, but it's hard to guess unless you have more concrete requirements in terms of LEs/memory/clock speeds.

Maybe if you pray they will make an Agilex-D PCIe developer kit that "only" costs $2k USD, requires tiny fans that sound like jet engines, and has 1 HDMI out.

You would easily eventually get into volumes of 2-3 million a year if you could get something out which is powerful enough for PS2 level re-creation.

The MiSTER project is already inspiring a generation to learn how to program FPGAs, those skills could be applied to improve performance in a lot of applications.

I'd like to know how many MiSTer owners there are in the world.

Part of me wants to say it's a lot, and part of me wants to say that the retro gaming community is peanuts compared to other FPGA consumers.

I suspect the same. My view is that the MiSTer FPGA crowd is very loud in the subreddits and discord channels of the world, but in reality most people using FPGAs in any significant capacity are much more tight lipped about it.

Yes, but recreating the PS2 is an order of magnitude more complicated than a PS1, which is still a massive undertaking for an individual. Even supposing we had a cheap enough FPGA, who would write the HDL to simulate a PS2?

The ps1 cpu was just a mips. Building a mips cpu with an fpga is a normal required undergrad project for a cs degree or it was a couple decades ago. I was feeling dismissive until I looked at the specs for the gpu and spu... That was some serious work for the ps1. The ps2 had that odd cell processor, or emotion engine whatever you want to call it. Its still basically multiple simplified mips cores but now all the stuff to synchronize them correctly? I'm surprised the ps2 emulators are as close as they are. Doing it all in hdl, and with the upgraded gpu, that is enough work that I wonder if software emulation fidelity wouldn't reach hardware fidelity before the fpga design did.

PS3 was Cell processor.. PS2 Emotion Engine..

Ah! The ps2 was still like 8 cores right?

I'll try to answer this, though my direct experience is only with Cyclone and Max 10.

The Mister uses the Cyclone V 5CSEBA6U23I7 built on TSMC 28nm. It has 110000 logic elements and also a hard ARM.

These are on Intel 7, so there a significant process improvement.

The smallest Agilex D has the same number of logic elements(1) and the largest has 6x as many (2). Note that Agilex tends to be much more expensive than Cyclone.

Realistic maximum clock rates on the Cyclone V are 50-200MHz, depending on the length of the combinational logic chains. For the Agilex I think that it is more like peak 600MHz. So I would guess say 25% faster and say peak 750MHz?

As to fitting all the logic for n64/PS2, I don't know!

1) Comparing these directly is not quite accurate.

2) https://www.intel.com/content/www/us/en/products/docs/progra...

did you really mean 25% faster or 4x faster?

If you really meant 25% you probably were not reffering to the clock speed/MHz, what were referring to?

I did mean 25% faster, though it was a guesstimate. That was comparing Agilex to Agilex D, not Cyclone V to Agilex D.

FPGA logic in simple terms consists of LUTs (look up tables, used to implement gates) and registers. The LUTs can be chained several times until they connect to a register. Registers are clocked at a frequency.

Now the max frequency is calculated using the maximum time from a register output, through a bunch of LUTs to reach another register. So it depends how long the chain is.

Its more complex than that in reality since there is also the time for the clock to propagate and to route the signals around. Fortunately the software takes care of that.

I don't really know how maximum frequency is specified in the specs, but I guess it'd be something like an ideal register->single LUT->register without much routing.

Would a Xilinx-based equivalent to MiSTer hardware have a better price-to-performance ratio?

Wow thanks. So for the Agilex D the answer is maybe, since the currently limiting factor seems to be number of logic elements and it would need at least a 3x upgrade in that regard [1] for n64. Well, one can hope that these become cheap enough for that.

[1] https://misterfpga.org/viewtopic.php?t=4535

You can in theory clock the Agilex/S10 parts up-to 1GHz, but something like 600-700MHz sounds more realistic, yes. (Note that this is in the same ballpark as what Virtex UltraScale+ can do too.)

Also, regarding point 1 -- and I'm sure you know this already, but this is for everyone else -- you have to be careful when talking about "Logic Elements" with most of the industry because, even when describing 6-LUT parts, Intel/Xilinx often list "Logic Element Count" to mean "Number of logic elements when considered on a normalized 4-LUT basis." Both Intel and Xilinx do this and I guess it kind of makes sense; only their highest end parts are non-4LUTs so they're the odd ones out when compared to everything else in the industry. So when you read "Number of LEs", they normalize it to 4-LUTs since that's what your competitors (or older parts) would use, when accounting for density.

For example I have a Stratix 10 card in my server that has "Millions of logic elements" when you look at the product tables, but that is taken on a normalized 4-LUT basis. There are actually "only" about 900,000 ALMs on the device, with each ALM being 8-input and fracturable. So TL;DR the numbers between the low-end Agilex-D part and the Cyclone part is maybe not that far off.

100%. For the record, the metrics I care about, and the first I seek out, is blockram cycle time and total device memory capacity. Unfortunately, unlike say Xilix/AMD, Intel doesn't publish that number directly, but Xilix/AMD's fastest for is > 800 MHz for the lovely Artix US+ and it has loads of memory.

The LUT count is a murky beast beast as you realistically cannot use them all lest P&R times shall be counted in weeks.

When you talk about "mid-range" in Intel's current product line up, that usually means the Arria 10 line. Those are typically around $1,000 for just the FPGA package itself, so I don't think we're realistically talking about something that's going to make meaningful impact on the hobbyist emulation market.

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