Sony's Nextorage Demos PCIe 5.0 SSD as It Enters SSD Market
tomshardware.com
tomshardware.com
From their press release:
Phison acquires Nextorage to strengthen customized high-end storage market
...acquired shares of its joint-venture company Nextorage Corporation from its joint-venture partner, Sony Storage Media Solutions Corporation
https://www.phison.com/en/company/newsroom/press-releases/ge...https://www.nextorage.net/en/company/
Existing Gen 4 product is very interesting:
"Dynamic SLC caching stores cache size up to 1/3 of the total storage area of SSD"
I want to bench this in a enterprise test. This is a lot of SLC and portends high random 4K writes that are very hard to achieve without something like a Pliops or GRAID array controller.
Claims are, "random read/write up to 1,000 K IOPS", which is three times that of most enterprise drives.
All this really means is that you use 100% off the SSD in 'SLC' mode, giving you 1/3 the usual space (since most SSDs are TLC these days). As you grow past 1/3 drive full, the drive reverts to TLC mode more and more and the drive slows down. Nothing innovative, as far as I can tell.
Otherwise what I care about is the minimum SLC size. Or, if it's significantly different, the SLC size when the drive is 80-90% full.
Edit: I think I get your query about "minimum SLC size": I imagine that the cache isn't scaling 1/3 of capacity across all SKUs 1-4TB.
By minimum, I'm talking about how a dynamic SLC cache is by definition using spare space in the drive. If all those cells are filled up with TLC data, they can't be used as SLC cache. But one drive might guarantee 5GB of SLC cache even when it's near-full, and another drive might guarantee 100GB, and those drives will have very different performance characteristics.
https://www.guru3d.com/news-story/phison-acquires-nextorage-...
Too bad Intel killed Optane.
https://blog.westerndigital.com/storage-class-memory-3d-nand...
CXL Optane wasn't going to happen because of the necessity for drivers in either block or direct access mode. Couldn't plug and play.
CXL itself is a good reduction in buss latency and there's been virtually nothing other words the occasional battery backed NAND DIMM on any memory buss, so SCL on CXL isn't going to be poor.
> CXL Optane wasn't going to happen because of the necessity for drivers in either block or direct access mode. Couldn't plug and play.
Drivers had nothing to do with that. Intel's Optane/3D XPoint could easily have adopted a CXL interface; nothing about the memory technology is tied to NVMe or Intel's DDR4-based proprietary persistent memory module interface. The only reason a CXL Optane didn't happen is because CXL wasn't going to magically make Optane profitable.
What confuses me is that the PCIe Optane drives launched at $4/GB and the second generation was only $2.30/GB on the biggest model.
Those prices gave those drives plenty of price advantage over DRAM. Was that all being sold at a massive loss? Why was DIMM Optane so much more expensive, and would CXL Optane have to be the same price?
Thx!
For my NAS uses the lower reliability of and SSD is not much of a concern. I still have a working intel SSD that is the first or second intel consumer drive they produced, it’s over a decade old.
Have you seen quality of the code that runs in most of the embedded devices firmware? It’s a huge surprise that any of the devices actually work. I don’t trust them a second to implement any secure encryption.
The problem:
- an operating system by necessity must have the crypto keys in RAM (which means it's vulnerable to a kernel-level exploit, a hardware-level exploit like Thunderbolt, or to a "freezing spray" attack)
- all I/O data will have to be shuffled between the SATA controller, RAM and CPU multiple times for decryption/encryption, incurring a (significant) latency penalty
Leaving the crypto operations to the SSD controller or an intermediate FPGA/ASIC removes a lot of these problems:
- the OS can wipe the memory containing the key information after passing them to the disk
- no part of the system can retrieve the key information past that point, and the disk controller can be built in a way that automatically wipes its internal RAM / plaintext key storage upon power loss
- there is no performance/latency penalty at all or at least significantly lower, the system gains back the ability to do DMA transfer (e.g. load GPU texture data straight from the disk into the GPU's RAM space)
Many countries and specifically authoritarian / totalitarian require certification of crypto for device to be sold on their markets. So it's easier for hardware manufacturers to either include none or just have single default option of possibly weak crypto.