The Next Incarnation of EDA | Hacker News Reader

The Next Incarnation of EDA

semiengineering.com

38 pointsmindcrime19 comments

I don't think that most software engineers understand how they good they have it with access to open source software. The most apt comparison I can think of to EDA is a mathematical computing environment (MATLAB, Mathematica, Maple, etc.) but an order of magnitude more constrained.

Everything in EDA is licensed. Simulators, emulators, synthesis, IDEs, formal verification, coverage, waveform viewers, and most post-silicon tools. You work with Intel/ARM? Any tools they make are licensed, too. You can't make CI/CD pipelines when you only have 3 $1000 compiler licenses for your whole company. Your JetBrains suite that costs $300/year for dozens of IDEs? It's not uncommon for HDL IDE licenses to be >$1000 for a single user.

Contrast that to most traditional software development, where the cost is solely in how much compute you're using.

I know that open-source EDA doesn't necessarily mean FOSS EDA, but that "free" part really is what's needed here.

And here I am designing physical consumer products thinking the people in EDA have it good.

A single license of CAD software with an FEA analysis add-on can easily run you $15k. Then the thought of shelling out for physical product testing will make you cry yourself to sleep.

The $1k figure quoted by OP is not indicative of the average price of licenses in my experience. There are plenty of tools that are $15k+ in the EDA world, and various engineers in chip design orgs are always battling about who gets to use them and when. There are whole teams in big SoC design shops dedicated to managing and procuring licenses.

I was pretty far removed from the license procurement and budgeting aspect of my last chip design job, but IIRC we were in the multi-millions per year in various EDA tool licenses. That figure may or may not have included IP licenses for pre-designed off-the-shelf subsystems.

I hadn’t even brought up IP licensing but you’re right. That’s another order of magnitude of cost and it’s incredibly important.

Same. We pay millions of dollars for our simulator licenses. Same again for physical design/layout licenses. These are for the standard ('best') industry tools, no IP. No idea what you get for $1k.

And Autodesk is a detestably evil company to boot.

Professional electronic design tools go through the stratosphere on pricing. There is lower demand than mechanical CAD tooling so they have to charge more to cover development costs. Lower demand also means that open source offerings usually pale in comparison to pro level tools from 20 years ago or more.

Unfortunately the OP is off by two orders of magnitude. Most VLSI EDA tool licenses start at about $100K per seat per year and go up from there.

If EDA tools were only $1K, we'd have lots of custom chips since a fab run in an old technology is actually $10K-$20K nowadays.

It depends on what tool licenses you're talking about. A single license for Questa is in the thousands of dollars range. But lots of VIPs or backend tools will be a lot more.

You can get pretty far with yosys, icarus verilog, various spice simulators and gtkwave, but I agree.

At least, interchange formats are pretty well specified (netlists, HDL, waveforms...), maybe except for the proprietary "Open Access" format.

If you suggest using those tools for most industry semiconductor work you’ll be laughed out of the room. I wish it wasn’t the case, but these tools aren’t good enough for most industry use cases.

I know almost nothing about this area. Just how much effort do you think it would take to get these tools to "good enough but no more"/MVP? Days/Weeks/Months/Years/Decades etc.?

From what I have seen of both the open source and commercial EDA software, I think it would take a well funded team somewhere around 4 years of development to catch up with the current state of the art. If we're talking about EDA emulation hardware, probably more like 6 years, since these usually have custom Basics designed for them.

Maybe you could cut a year off of those and still have something that is good enough but not state of the art.

Aside from what was already mentioned in another comment, one of the largest things lacking in this area is not having dedicated support. These tools are maintained by only a few individuals, and if you need a feature of bug fix, you either need to implement it yourself or wait a long time for a fix.

If you need a feature or bug fix from Cadence, Synopsys, or Mentor, I've usually had releases that fix the issue within a week or two.

The article seems to imply that EDA vendors contributing to a common open source project is where EDA ought to go moving forward. That's a step in the right direction because it'd fix this support issue I mention. But it probably won't fix the cost issue.

The problem (or perceived, I guess) with yosys is that it is not production safe. It does still, from time to time, produce catastrophic synthesis errors. If you're going for tapeout, a synthesis issue due can cost millions in wasted parts, and so most in industry are willing to pay the astronomical costs of whatever synthesis tools of choice because they are significantly less than the cost of an error. For FPGA stuff though? Yeah, yosys all the way--I'm willing to forgive the worse optimization for it being FOSS :)

I understand your point, though I have never done synthesis at that scale.

Still, with yosys, Verilator and other tools, you can have some form of CI. Using multiple simulators can reduce the number of bugs, and no one in their right mind would spend >100K for a tapeout without checking it with all available tools.

I can see day-to-day development being performed with yosys and others, with punctual verification (including the final one) on other simulators.

There's plenty of advantages: local/offline development environment, CI, multiple tools to help home in on issues, better perf in some cases, no fighting over license seats (heck, even one seat should be enough).

Now, if companies would donate a few percent of their license costs to FLOSS alternatives, the software landscape would be very different indeed.

I know industry gets away with it, but I think a post synthesis simulation run is in order until the tools can prove that their output is correct.

I really hope Lattice ends up leaning into the open source symbiflow toolchains, it is amazingly awesome to have a decently sized FPGA that run Linux, that could even self host it's own firmware compilation. (VERY SLOWLY!)

Electronic design automation apparently, not exploratory data analysis.

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