Even if you don’t have an FPGA, you can run these hardware designs on your PC with SDL and Verilator.
It’s really simple to set up: https://projectf.io/posts/verilog-sim-verilator-sdl/
It’s really simple to set up: https://projectf.io/posts/verilog-sim-verilator-sdl/
This was my biggest shock when first working with FPGAs, while naively using a software mentality. Most everything had to be re-written once the simulations were done.