Very nice to see RISC-V growing like that and being in the area of interest by big names such as Google and Intel. Open solutions are critical for risk management but I wonder if desktop/server RISC-V processors are also planned.
deterred by the size of the profits for the winners, and the losses for those who do not compete in global markets.. yet I suggest there are few things more interesting than a personal, general purpose computer
But I think more importantly, there will be no demand until someone makes a RISC-V CPU that can actually compete with Intel, AMD and Apple on performance.
$100 Laptops, $70 phones and $50 tablets will be a big target for RISC-V.
There are some open source riscv cores, but the paid ones make money for a reason
If RISC-V doesn't see the development for upmarket products it's not going to magically take over the downmarket segments. No one footing the development bill is going to selling $50 tablets.
Now I know that doesn't sound like much. Don't kid yourself into thinking Apple Silicon M1 and M2 came from nowhere, though. If it wasn't for growing capability in the ARM lines in other products Apple would not have been so likely to invest in it for their new technology, Rosetta or no. Exynos Chromebooks and such led the way to ARM Macbooks the same way the IBM PC led to displacing DEC and Sun workstations, then minicomputers, then x86 servers replacing most other servers in the DC.
I think chrome books had very little to do with it. A lot of the work had already happened with the PowerPC switch. On the processor front, Apple’s arm processors aren’t at all like exynos chips that use standard arm cores. I would say that the apple silicon macs are more influenced by iPhone and iPad success than anything else, especially since iOS already runs a lot of macOS
There's a whole world of ARM processors out there. The ISA, packaging, software, and expertise around it everywhere in the world helps make that ecosystem stronger. Before ARM there was Intel, and before Intel was PowerPC, yet even before that there were the 68000 series Macs. And before the Mac, there were the 65816 in the IIgs and the 6502 in the Apple II. Don't be surprised if Apple is an early adopter of RISC-V for support processors. If they decide they've made them performant enough after a few years of that, don't be surprised if they use them as CPUs and stop needing to license cores and ISAs from ARM at all.
But I can promise you one thing. Apple didn't look at the 18 MHz v7 cores from Cirrus Logic in the Psion Series 5 and immediately decide they could make a mainstream desktop CPU out of it. The competition of companies like Samsung, Qualcomm, and Broadcom in consumer electronics has a lot to do with how ARM cores became suitable for Macbook.
Given that and in the absence of a clear rationale I find it hard to see why Apple would want to to incur the costs of a move to an ISA it’s had no influence over - certainly not to save an immaterial licensing fee.
It’s more likely that Psion looked at the 20 MHz ARM cores that Apple shipped in the Newton and decided they could make a Psion with that.
Psion adopted a CPU Apple was using in, AND A COMPANY THEY OWNED developed for, the Newton and eMate, not the other way around. The ARM710 used in the Series 5 was the same as Apple used in the eMate.
Apple plays a long game, but saying they funded ARM in the mid 1980s so they could slowly grow those cores by themselves for themselves in 2020 and later ignores a whole lot of history about both Apple and ARM.
Apple knew that when it invested in Arm and chose Arm for Newton, for the iPod and the iPhone (note Apple has been selling Arm based products continuously since 1993 apart from 1998-2001).
It’s no accident that there is an Arm based CPU in the Mac now. Apple’s most important Mac is the MacBook and performance per watt is key. Until someone can offer an architecture that demonstrably does much better on this metric Apple will stick with Arm.
I can definitely see that hobbyist market and future Pi-like devices moving to RISC-V, but I'm less certain about mainstream use unless Windows and Mac (or maybe even Android and ChromeOS) really decide to move over.
And I know of 3 families that have pi based desktops at home, and use them as desktops. (One of those has a person that works in IT in it.) I don't know anybody that has "experimental desktops" that they use only to thinker with, AFAIK, when people assembly a desktop, it's because they want to use as a desktop.
One thing that RISC-V enables is open source hardware CPUs. There are quite a few people who're upset by stuff like the Intel Management Engine IME making them distrust their personal computer.
These folks don't really have any options that fit their criteria right now.
Some RISC-V CPU could fit in there.
But over ten or fifteen years? Very possibly. And if not porting apps directly to RISC-V, then porting them to WASM and letting browser vendors optimize WASM performance on RISC-V.
But these days, you have advanced 600MHz microcontrollers with simple GPUs, and full-featured CPUs which get used as an embedded platform. You can even build a Linux kernel for no-MMU platforms.
It's a fuzzy line.
High end OoO cores in other ISAs are BREAKING DOWN complex instructions into µops. RISC-V is pre-broken down. The one exception to that is current x86 and ARM cores DO do instruction fusion, to combine a compare with a following conditional branch. Which is a singe instruction in RISC-V in the first place. SO it is actually the other way around.
Low end cores shouldn't be doing either fusion or breaking down into µops. They are supposed to be as simple as possible, and doing either of those is a complication using significant silicon area and energy.
There might be a place for instruction fusion in mid-range cores. Things in the ARM Cortex A53 / A55 / A510 range. The most popular RISC-V core in that segment, the SiFive U74 (used in the HiFive Unmatched, BeagleV Starlight, VisionFive v1, VisionFive 2, Pine64 Star64 .. and probably more yet to be announced) doesn't fuse multiple instructions into one instruction, but it does pair a forward conditional branch past a single instruction with that following instruction. Both instructions still exist, they each go down one of the two execution pipelines side by side, the same as if the branch was predicted not-taken. At the final pipe stage if the branch turns out to be taken, instead of taking a mis-predicted branch penalty and flushing the pipeline, the U74 simply does not write the result of that following instruction back to the destination register.
That's the closest any currently shipping RISC-V core I know of comes to instruction fusion.
"crazy difficult to implement levels of instruction fusion" does not exist anywhere, and is not needed. It's just an idea from an academic which doesn't actually exist in the real world, at least at present.
Other features you're likely to want are also included in the specification, so if you want to write code that uses for example the B bit manipulation extension or the V vector extension (which is scalable with vector width as well, unlike SSE/AVX) you just have to check a standardized 'CPUID' bit and can run your code, and otherwise fall back to other code.
I also believe that the spec may let operating systems hook these instructions and provide fallbacks so application developers don't have to, but I'm not too sure on the specifics of the privileged ISA of RISC-V.