Yes. Process changes, transistor geometry, dielectric materials, were all things that people expected to change. That customers would stop using TTL was pretty avant-garde, but when ASICS became "affordable" (basically custom chips for non-chip companies) it was obvious that volume manufacturers would condense a bunch of TTL into a single package just for cost reasons.
But fundamentally electrons and 'charge' are quantum in nature and even in the 80's if you're transistors were "too close" you could get electron tunneling between them. So I, and others, assumed there was a really hard limit on how small you could go (and it was likely above 100nm rather than below it). And of course now hardly anyone used old 90nm tech, I think 40nm is the current "jelly bean" process but I freely admit I've not looked at the geometries used in the vast Chinese IC market of "support" chips.