It's not even that. Nothing in a modern process node is as small as the node size, and in fact with modern processes it's not even close. I just checked, and per some reference on wikipedia TSMC 3nm's metal pitch is expected to be 24nm (so, ~12nm wide metal "wires" on the lowest level of interconnect are the smallest things you'll see on a picture).

What's been happening is that fabs have been exploiting more and more tricks to increase transistor density while still using the larger feature sizes. So flat transistors became finfet's, increasing their gate area and allowing chips to use fewer of them for the same silicon area, etc...

So read "3nm" as "a process with the same transistor density as you would expect had some ancestral ~90nm process been shrunk by a factor of 30".