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Comment by judge2020 | Hacker News Reader

judge2020

Note that 3nm and the rest of the process names in the past decade don't actually measure the size of the transistor - it's all marketing[0], and is why Intel is dropping the "nm" naming in favor of "Intel 7, Intel 4, Intel 3, Intel 20A, Intel 18A"[1]. However, maybe someone can link to resources that explain the potential [quantum] hurdles they have to overcome as they've increased density and performance.

0: https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-n...

1: https://www.anandtech.com/show/16823/intel-accelerated-offen...

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Okay but who they are fooling exactly? It's not like an average soccer mum shops for CPUs and choses the 3nm because she is impressed with the 3 nanometre transistor gates, right?

Are they after investors or traders? Why they don't call it something like superlaser 9000 and the next year hyperlaser 10K speedmaster?

I think it's mainly for investors yea. They don't want people reading articles to see that the competitors numbers are better than theirs.

> It's not like an average soccer mum shops for CPUs and choses the 3nm because she is impressed with the 3 nanometre transistor gates, right?

No but enthusiasts (read: gamers) do. A lot of PC industry marketing nowadays is geared towards retail PC builders, who are very impressed by tech jargon.

But tech media outlets like gamers nexus always remind viewers that intel 7 is really intels 10nm, etc

Even though the process sizes aren’t objective or comparable across manufacturers, they do indicate meaningful improvement in sizing / density from a specific manufacturer.

It’s all about transistor density and newer nodes deliver that. Nobody cares about gate size.

Well how does transistor density go up without transistor sizes getting smaller?

Companies spend millions on brand marketing and that is the result. Needs to be short and memorable, your suggested naming is too long and more than 2 syllables.

Yeah, I don't think that 5nm, 3nm are chosen for shortness.

The actual process name is very long, 5nm and 3nm is short and easy to remember.

A large part of the current usage of the terminology comes from historical momentum. It used to be the case that transistor size was fairly well correlated with performance and capability. Moore's Law was well-known and a simple transistor size was a good, easy way to approximate performance potential for power consumption, speed, capability, complexity, etc... That single number started getting slapped on all of the marketing and documentation as a somewhat useful "overall performance rating" substitute. Companies got used to showing it off. Consumers came to expect it. The real, actual usefulness of the number diminished slowly enough that it's just continued so far. And marketing doesn't like removing stuff that they think makes their products look good.

It's also still useful as an identifier to distinguish between one node process and another, so it's not entirely pointless, even if the nomenclature is meaningless.

My friends from marketing tell me that the target here are the press, specifically the industry press. In a competitive market you want to make it "hard" or "easy" to compare your product to your competitors product or service, if you're the leader you want it to be 'hard' and if you're the competitor you want it to be 'easy'.

I originally asked this exact same question of the guy at AMD who started talking about their x86 chips in "equivalent" megahertz because they the actual clock rate was slower but they had a better instruction per clock (IPC) and so got more done per second than their Intel counterparts, but Intel was winning in the "Megahertz race" because that was what the press was fixated on using to describe the "leading" chips. Anyway, if you're a leader and and you can get the press talking about something your competitor isn't (or can't) do, then you "win" the perception of being ahead.

In semiconductors, this has been very effective at getting the press to see Intel as "behind" because their "nanometer" number was stuck in the double digits while "more advanced" fabs were already in production on lower nanometer number processes. (Note the scare quotes are all just to indicate topics that both TSMC, Samsung, and Intel would have different takes on the current state of the art here).

They really should just do transistors/mm^2 or transistors/mm^2/watt or something.

The problem with that measurement is that you get extremely different numbers depending on what you're making. e.g. the density of memory is massively different to the density of logic.

I don't think that's necessarily problematic anymore then measuring fluid viscosity is problematic. Once someone start's getting into debates over the size of transistors on microprocessors then you are already getting pretty wonky and are going to need some science to describe things anyways.

So you pick something relatively standard (like an SRAM cell), and you use that.

There was a concerted effort some time back to formalize a standard measurement of process density using something like "million transistors per square centimetre" by a standards organization. (IEEE?) It wasn't a perfect measurement but it was a lot better than width. It failed so completely that I can't even Google it any more. The awkward name probably didn't help.

edit: it's "MT/mm2". Some people actually use it, but more in the informal sense that has the problem you espoused rather than the formalized one, which I still can't find.

A lot of Wall Street seems to have issues with non GAAP accounting metrics like Annual Recurring Revenue (based on the the few earnings meeting I've listened in on), I don't have high hopes that this would work.

That wouldn't capture the fact that there are fundamental physical barriers being run into. "Smallest feature size" is a perfectly adequate metric until things get complicated. Replacing an insufficient simple metric with a different one insufficient metric isn't the right solution imo.

Well current is proportional to W/L, and W and L is area

We can always increase W, but decreasing L requires technological advancements

So I’m not sure on the value of area (W and L), L alone is more relevant (for the reason I said above)

we are dealing with finfets / GAA now which are not the same as planner transistor, but I guess there should still be relevance in L and W because these measurements are important even for resistors

So probably some sort of equivalence between a FF and a planar transistor should be given to name the nodes

Like this: https://ieeexplore.ieee.org/document/9063714

Each node will have many sets of transistors depending on what you want in the tradeoffs between power/density/performance. Typically a half dozen or so options.

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