darn, not quite the HLS the headline suggested.
https://dlang.org/blog/2017/07/17/dcompute-gpgpu-with-native... With DCompute you can use metaprogramming to generate shaders alongside D code for GPUs, really want to try it with an FPGA. Similar things probably exist for rust as well.
Getting the data back off the FPGA into the program is undefined behaviour, though.
It's not a "very contrived SYCL ugly-ugly-ugly pipeline"--Intel's oneAPI explicitly has a FPGA backend for its SYCL compiler: https://www.intel.com/content/www/us/en/develop/documentatio...
I also find oneAPI kind of ugly although it was a while since I really dug into it.
I've wondered how much work it would be to get Rust->SPIR-V->OneAPI compiling, but it sounds like an exercise in masochism so haven't gone down that route yet.
In software we want nice abstractions and so on, with FPGAs if those abstractions are even possible you probably can't afford to write them.
I spoke to an ASIC designer recently, the EDA industries weird.
The big thing with SYCL and oneAPI and so on for me at least is that you have all this stuff bolted onto C++. C++'s ability to do generative programming is just not as good as it's competitors, that and C++ just being a bad language. If things are more language-agnostic than I realize then yippee
The clever thing about the DCompute project that I linked above is that it uses a simple but powerful introspection system (provided by D, could really be any competently designed language) to pick up the right stuff and generative the compute kernels in the background for you.
(The commercial ASIC design world is very conservative, with some good reasons and some bad, and tends not to use either advance, preferring the VHDL/Verilog of our ancestors)
That said, loops aside, most compiler IR is a sort of dataflow graph which could reasonably be synthesized into hardware. But most control flow does not map very well.
Higher-level HDLs such as Chisel (although I have never used it) instead abstract directly over standard HDLs like Verilog or VHDL. These abstractions are simpler because they do not alter the fundamental design ideas; they just offer increased flexibility (for example VexRiscv, which is written in SpinalHDL and has most functionality in 'plugins' which extend CPU components, which is a very powerful form of metaprogramming that is not possible with Verilog).
If your issue is with Scala, there's other HHDLs such as Clash (based on Haskell) or Migen and Amaranth which use Python.