The mirocode is generally a sequence of uOps. But in Intel's case, there seems to be a more complex mechanism, called XuCode, that generates the uOps sequence. The XuCode ISA seems to be based on x86-64, as Intel says [1]:
> XuCode has its own set of instructions based mostly on the 64-bit Instruction Set, removing some unnecessary instructions, and adding a limited number of additional XuCode-only instructions and model specific registers (MSRs) to assist with the implementation of Intel SGX.
PS: Decoding of the XuCode microcode can potentially give precious information about uops encoding
PS2: You can find more information on uops encoding in another work from the same team [2].
[1]: https://www.intel.com/content/www/us/en/developer/articles/t...