Concerns over mask register design in RISC-V Vector Extension v1.0

Also worth reading this issue: https://github.com/riscv/riscv-v-spec/issues/617

I think it's a fascinating discussion. There's been some disquiet at this design choice amongst a minority for a while from what I can tell. Who will be proven right? Perhaps this will be one of the warts of RISC-V we're looking back at 10 years from now wishing it had been dealt with better. Perhaps instead it'll prove to be a sound design decision.

All the established ISAs have various warts that make hardware implementation a pain or compiler writing harder than it should be. The decision making for those and their genesis has all been behind closed doors. Are we seeing a similar misstep now happen in the open?