Doubtful. PCIe Gen 5.0 x16 over DDR5 is a huge cost increase, a huge latency increase, and only a minor bandwidth increase (about double after accounting for protocol overhead.) At that point, you might as well widen your memory bus and use 2 DRAMs. The memory controller doesn't get much more complicated because both chips share a CA bus, and the DRAMs are cheaper. I don't work for a DRAM vendor, but I would imagine that the front end logic in the DRAM (the DDR controller inside the DRAM) uses way less than half the die area that a PCIe Gen 5.0 x16 EP would use.