Comment by jecel | Hacker News Reader

Comment by jecel | Hacker News Reader

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You might find some aspects of my SiliconSqueak 3 design similar to your ideas. The details for the instruction set can be found in the appendix of this 2015 text:

http://www.merlintec.com/download/jecel_phd_deposited.pdf

The basic idea is that each instruction mentions two operand registers and one destination register. There are 4 kinds for the first operand and the destination:

t0 - t31: actually map to the special stack cache. Changing the frame pointer will remap them to a different area, possibly causing a line to be reloaded.

i0 - i31: actually map to the data cache as the first words of the receiver. Changing the self pointer will remap them to a different area.

s0 - s31: control registers for DMA-like logic that allows values to be streamed to other processors or to memory

x0 - x31: a mix of registers that control the hardware, including the frame pointer and the self pointer. Also allow pushes and pops to the stack.

The second operand can be these as well, but can also be several kinds of constants and can (L0 - L31) fetch the literal values in the current method, which also allows indirect access to globals.

The stack cache operates on linked lists of 32 word blocks (the current frame can span two such blocks) so the hardware to map tN to a cache word only needs a five bit adder

Hey, thanks! I'll take a look; I've been appreciating your work for decades and didn't realize you'd already gotten your Ph.D. Congratulations!

t0-t31 and i0-i31 do sound very similar, although off the cuff it sounds like you're designing for a processor about two or three orders of magnitude larger, like 400,000 to 4 million transistors rather than 4000.

The reason I was thinking XORs instead of adders is that if you have, say, 16-bit addresses computed from a 16-bit base pointer and a 5-bit offset, it's true that you only need five full adders, but you still need 11 more bits of carry chain (or 10 bits if your 16-bit addresses address bytes and your offset units are 16-bit words, as is usual in Smalltalk-80).

Actually, my school has a very strict deadline and I missed it so didn't get the PhD. But there is that text and the slides of my presentation:

https://prezi.com/yhw-a3i0rnri/adaptive-compilation-for-an-o...

The focus for SiliconSqueak 3 was to have a small die area for the version without the ALU Matrix coprocessor. The inclusion of a total of 20KB of caches does bump up the transistor count by 20*1024*8*6 = 983,040 transistors all by itself though these tend to be far more dense than logic transistors. The rest of the processor is reasonably small.

The stack cache is organized as 32 word blocks that are aligned in memory on 32 word boundaries. At any instant pseudo registers t0 to t31 are covered by two blocks, named low and high. Adding the register number to the bottom 5 bits of the frame pointer gives you a five bit result plus carry. The carry selects between the low and high blocks while the five bit result is the word within that block.

When the frame pointer moves out of the low block, new low and high blocks are selected by following a linked list. This allows stack blocks from multiple threads to live side by side in the cache.

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