Toward Democratized IC Design and Customized Computing

I found the below point very insightful, which compares the output of HLS (High Level Synthesis) without and with small changes:

> For example, for the simple 7-line code of the one-layer convolutional neural network (CNN) widely used in deep learning, shown in Figure 1, the existing commercial HLS tool generates an FPGA-based accelerator 108x slower than a single-core CPU. However, after proper re-structuring of the input C code (to tile the computation, for example) and inserting 28 pragmas, the final FPGA accelerator is 89x faster than a single-core CPU (over 9,000x speedup over the initial unoptimized HLS solution).