Yay for 5ghz and Risc-v. Only other thing is ble with actual ble power consumption from Espressif.
Speaking of which, Nordic bought out that WiFi startup late 2020 but have been silent on their WiFi mcu since
Speaking of which, Nordic bought out that WiFi startup late 2020 but have been silent on their WiFi mcu since
Some benchmarks on the earlier ESP32-C3 at https://hackaday.com/2021/02/08/hands-on-the-risc-v-esp32-c3... ; it seems it has the same core as the new ESP32-C5 except it's clocked at 160 MHz instead of 240 MHz. Extrapolating those ESP32-C3 benchmark results out to 240 MHz would suggest it's a bit spiffier than a single core Xtensa ESP32 but not enough to catch the dual core xtensa.
I would assume that the wifi stack is hardware scheduled on that core with dedicated scratch ram, and that the rest of the cache and cpu cycles are granted to the user visible core only while not needed. I think a whole lot of applications didn't use the second xtensa core on the earlier parts.
The cores were even named Core0 - PROtocol and Core1 - APPlication in the initial ESP-IDF design, where the core affinity model was going to be more strongly enforced (thankfully they backed off on this idea and now it is fully configurable SMP).
why? You as a user get 2x less computing power and celebrate it because vendor saved on licensing?