Samsung expected to announce mass production of 3nm chip next week
en.yna.co.kr
en.yna.co.kr
> The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption, However, there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node. For example, TSMC has stated that its 3 nm FinFET chips will reduce power consumption by 25 to 30 percent at the same speed, increase speed by 10 to 15 percent at the same amount of power and increase transistor density by about 33 percent compared to its previous 5 nm FinFET chips.
The same article states that transistor densities for Samsung 3nm will be 202.85 Million transistors per mm2 and for TSMC 314.73 Million transistors per mm2 so quite a big difference.
If the transistors were 2D and square then that makes Samsung's 3nm transistors actually 70nm, and TSMC's 56nm according to my maths!
With chip process node "nanometers", I assume that "the other limit" (the role taken by the lens in the camera analogy) is the size required by transistors if we had infinite resolution. Lower "nanometers" will allow us to get closer to that hypothetical best, but the benefit will be smaller and smaller.
I'm not sure how this changes the geometry, or the relevance of "3nm."
"The next-generation 3nm chips will be built on the Gate-All-Around (GAA) technology, which Samsung said will allow up to 45 percent area reduction while providing 30 percent higher performance and 50 percent lower power consumption, compared with the existing FinFET process."
"N2 will see TSMC switch to a nanosheet transistor architecture rather than the fin field-effect transistor (FinFET) design that has been standard in the industry for some time in order to deliver improvements in performance and power efficiency.
"The nanosheet architecture involves the electrical current flowing through several stacked layers of silicon that are completely surrounded by the transistor gate material. IBM claimed to have made the first 2nm chips using nanosheet technology last year."
https://www.theregister.com/2022/06/17/tsmc_details_2nm_node...
"Big Blue today claimed this is “a breakthrough in semiconductor design” using nanosheet technology. That involves layering three sheets of material to form a stack containing an NMOS transistor on top of a PMOS transistor, rather than placing them side by side, commonly called a gate-all-around design. It's a step on from today's 3D FinFETs...
"It should be noted that although it’s described as being 2nm, the size of the process node is more of a naming convention to show it's smaller and more advanced than its previous 5nm design. No part of it is 2nm in size. The actual transistor gate length is 12nm."
https://www.theregister.com/2021/05/06/ibm_2nm_semiconductor...
I wonder why IBM is putting so much money into GAA when they don't even own a foundry, and their previous foundry partner has little interest in making anything smaller than 14nm.
>Samsung’s issues with yield are concerning. It’s said that the yield of the Qualcomm Snapdragon 8 Gen 1 manufactured by Samsung Foundry is 35%. What that simply means is that out of the 100 pieces that are manufactured, 65 are defective. The yield for Samsung’s own 4nm Exynos 2200 is shockingly said to be even lower than this.
https://www.sammobile.com/news/samsungs-horrible-yield-qualc...
Hopefully this will put commercial pressure on better computer science, algorithms and software efficiency.
(My experience is that Whirlpool/Maytag appliances now all have a gratuitous circuit board with parts that reliably burn up after warranty runs out, requiring a $100-300 replacement. In my washer, the top actually blew off of a LNK305 voltage converter, exposing the chip inside, along with several traces and various other parts.)
> TSMC, the world's largest contract chip manufacturer, said it will begin mass production of 3nm chips in the second half of the year
Although to other very recent sources:
> TSMC has detailed its chip development timeline at its 2022 TSMC Technology Symposium[: t]he Taiwan-based chipmaker is introducing 3nm chips in the second half of this year and will bring 2nm technology to the world stage in 2025
https://www.gsmarena.com/tsmcs_3nm_chips_coming_in_2023_goin...
TSMC N5: 185.46
TSMC N4: 196.6
TSMC N3: 314.73
Samsung 5nm: 133.56–134.9
Samsung 4nm: 137–145.7
Samsung 3nm: 202.85
I drove past a Micron Technology building last month, and had to reflect on how many square microns a 6502 would take, nowadays. Not counting TTL drivers, looks like around 4x5 microns. An original ARM would fit in like 10x20 microns. Invisible either way.
More like "free market competition with state intervention".
Speaking of which, Europe needs to get moving. Europe badly needs local factories and ideally local companies building advanced chips.
Yeah, Europe will again fall behind in tech, especially sine we're currently busy withering a war on our borders, rampant inflation, and an energy crysis.
We have some local companies that are suppliers to the semi industry like Zeiss, Asml, Trumpf.
Intel is investing €17 billion in a new fab development at its Leixlip campus. With this new fab we double the manufacturing capacity available in Ireland and enable the production of Intel 4, the company’s most advanced process technology.
Probably the US would be substantially less interested in defending Taiwan if TSMC was not there.
Is the chip in my coffee maker ever going to be made using EUVL?
It's only the certain layers that are printed with EUV. Typically these are the first one or two metal layers (connecting the individual transistors) and the vias between them.
This is also a new physical layout of transistor (gate all around) compared to fin-fet previously, so we can expect those other calculations like speed and efficiency to work differently on this node.