I agree, dissipating 950 Watts over such small area seems infeasible. Maybe with a phase change cooler.
phase change is an awful idea for such high power. It's just fake.
Multiple clock regions is one option. Others pointed out large silicon areas. We also don't know how the packaging is done - it may be a bunch of smaller, 32-core, chiplets separated by interposers or memory controllers and IO modules running at lower speeds.