This reminds me when I first started getting into FPGA's... a looong time ago. I to code verilog by using this cool feature in Quartus, which was the design software for then Altera FPGA's (now Intel). It had this feature where you could draw a schematic using 7400 logic and it would turn that into the rbf file to config the FPGA. I just thought that was so cool at the time and it was a nice entre into that world.

Later, I got curious, and it had feature to output the 7400 schematics to verilog HDL code. I became very interested in that and eventually learned verilog from the schematic capture and some online tutorials. It wasn't long and I left schematic capture behind. But I thought it was a great way to get into HDL coding.