Details on AMD's Quirky Chipset Solutions for AM5

AM4 cpus have an x16 for GPU, an x4 for NVMe storage, and an x4 for chipset, according to the article, AM5 cpus will have an x16 for GPU, an x4 for NVMe storage, and adds an x4 for for USB4 or more NVMe storage, and then an x4 for chipset, plus whatever the USB stuff means.

The rumored chipset takes that x4 and offers two x4s, four sata/3.0 x1 ports, and 6 usb3, six usb 2 ports.

There were a bunch of different chipsets for am4, most of which didn't have more connectivity than that. If you build the x670 link two of the new chipsets, and consider the added x4 from the cpu, you still have pretty similar connectivity as the x570, but you only have 12 lanes squeezing into the x4 for chipset instead of 16. There's certainly a discussion to be had about the CPU lanes being 5.0 and the chipset lanes (including uplink to the CPU, apparently) being 4.0; but while there's not much in the way of PCIe 5.0 devices, it's mostly hypothetical. If PCIe multiplexers weren't immensely expensive, the 24 CPU lanes at PCIe 5.0 would be equal to 48 lanes of PCIe 4.0 (plus 4 more for the chipset), and pretty close to the Zen2 Threadrippers's 56 + 8. Lack of cheap multiplexers means that's not really how the cookie crumbles though.

Maybe the pricing you expect will be at a level that I am going to ignore anyways, but I think AMD may be reducing features and pci-e lanes because Intel has been doing just fine not giving away the kitchen sink in that area, at least from what I observe. Isn't intel kind of dragging their feet with any new HEDT lines?

On the contrary, compared with the previous generation, the AM5 socket has more PCIe lanes, because it has 4 additional PCIe lanes, to attach directly to the CPU a Thunderbolt/USB4 controller, for maximum performance.

The changes are strictly in the chipset, which will now be able to provide more PCIe lanes than before, on more expensive motherboards with 2 southbridge chips, but with the price that the extra lanes will pass through an additional PCIe switch, so they will have a greater latency and their throughput can be diminished by congestion, when all the peripherals are active simultaneously.

Nevertheless, with 64 Gb/s links between chips (4 x PCIe 4.0), few peripherals will be fast enough to saturate the links and cause congestion, i.e. typically only the extra SSDs or extra GPUs, besides the primary GPU and the primary SSD, which are attached directly to the CPU.

So the extra SSDs and the extra GPUs should be preferentially attached to the first southbridge chip, not to the second. This is the change about which the users of the new AM5 motherboards must be aware.

While the daisy chain is interesting, it doesn't sound like it gets you much at the end of the day and will double power usage (which was a real sore spot with x570 vs the asmedia chipsets) The dual chipset sort of seems like it's just a luxury item without a purpose in most cases. Maybe we'll see some interesting designs with server oriented boards but doubling the power usage doesn't seem worth what it will get you to me.

Are any of the typical uses for those IO lanes latency-sensitive enough for that to matter at all? Consumer-grade networking, SATA storage, and most USB use cases all involve latency high enough that one more PCIe switch wouldn't be noticed.

https://www.tomshardware.com/news/amd-x670-motherboard-diagr...

If you could have your CPU placed symmetrically in the middle of the board with slots, ports etc both above and below so they don't get too long traces then maybe? But that would go against the ATX spec.

I also wonder how often communication happens from one device direct to another without touching CPU? Is that a thing? DMA has been a thing for many years but with the memory controller on the CPU communications would still have to get there.

Of course, the chipset itself has nothing to do with what connectivity is provided to the PEG slots since those run straight to the CPU - this is market segmentation in action, the CPU simply won't turn on those feature-bits if you don't pay for the premium chipset.

Also, as noted, on AMD the chipset has nothing to do with anything anyway. It is just an IO expander, it doesn't boot the CPU or do anything like that, and it is entirely uninvolved, out of the loop entirely, when the CPU is talking to things that are attached to PEG direct lanes.

No, because PCIe works completely differently from RAM. PCIe is a packet-based protocol that's very latency-tolerant. (Multi-lane PCIe links may require deskew but that's a standard feature that has existed all along.) I think it was Marcan who tunneled PCIe over RS-232 and the chips didn't even notice.