Comment by kalleboo | Hacker News Reader

Comment by kalleboo | Hacker News Reader

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The source is a former Apple engineer (now at Nvidia apparently)

https://twitter.com/stuntpants/status/1346470705446092811

> arm64 is the Apple ISA, it was designed to enable Apple’s microarchitecture plans. There’s a reason Apple’s first 64 bit core (Cyclone) was years ahead of everyone else, and it isn’t just caches

> Arm64 didn’t appear out of nowhere, Apple contracted ARM to design a new ISA for its purposes. When Apple began selling iPhones containing arm64 chips, ARM hadn’t even finished their own core design to license to others.

> ARM designed a standard that serves its clients and gets feedback from them on ISA evolution. In 2010 few cared about a 64-bit ARM core. Samsung & Qualcomm, the biggest mobile vendors, were certainly caught unaware by it when Apple shipped in 2013.

> > Samsung was the fab, but at that point they were already completely out of the design part. They likely found out that it was a 64 bit core from the diagnostics output. SEC and QCOM were aware of arm64 by then, but they hadn’t anticipated it entering the mobile market that soon.

> Apple planned to go super-wide with low clocks, highly OoO, highly speculative. They needed an ISA to enable that, which ARM provided.

> M1 performance is not so because of the ARM ISA, the ARM ISA is so because of Apple core performance plans a decade ago.

> > ARMv8 is not arm64 (AArch64). The advantages over arm (AArch32) are huge. Arm is a nightmare of dependencies, almost every instruction can affect flow control, and must be executed and then dumped if its precondition is not met. Arm64 is made for reordering.

> > M1 performance is not so because of the ARM ISA, the ARM ISA is so because of Apple core performance plans a decade ago.

This is such an interesting counterpoint to the occasional “Just ship it” screed (just one yesterday I think?) we see on HN.

I have to say, I find this long form delivery of tech to be enlightening. That kind of foresight has to mean some level of technical saaviness at high decision making levels. Whereas many of us are caught at companies with short sighted/tech naive leadership who clamor to just ship it so we can start making money and recoup the money we’re losing on these expensive tech type developers.

I think the "just ship it" method is necessary when you're small and starting out. Unless you are well funded, you couldn't afford to do what Apple did.

Either way, "designed a new ISA" really should be "came up with yet another cleaned-up MIPS RISC". Does it really matter who did the work?

AArch64 does not resemble MIPS at all (beyond the fact that both use fixed-length instructions and separate register-register and load-store instruction groups; these RISC principles had already been used in IBM 801 about 5 years before MIPS, and then they have been used in more than a dozen of other CPU architectures, many of which are more similar to AArch64 than MIPS is).

Therefore, there is no basis for saying that AArch64 is a cleaned-up MIPS-like ISA. Only RISC-V is a MIPS-like ISA.

One of the few features of AArch64 that can be said to be similar to MIPS was its main mistake.

In the initial ARMv8.0 version, the only means provided for implementing atomic operations was a load-and-reserve/store-conditional instruction pair.

This kind of instruction has been popularized by MIPS II, but it had not been invented by MIPS, but by Jensen et al. (November 1987), for the S-1 AAP multiprocessor.

While this instruction pair allows the implementation of lock-free/wait-free data structures, it can be extremely inefficient for implementing locks in systems with many cores (because progress is not guaranteed), so in the ARMv8.1 version the initial mistake has been corrected, by adding atomic instructions of the type fetch-and-op, besides the MIPS-like LL/SC pair.

The complex features of ARM64 were not newly designed by and large, they were mostly carried over from ARM32 - mostly to take advantage of shared ARM32/ARM64 implementation. Much of the actual design work involved in ARM64 was simplification and things like adding a zero register to the ISA, which is pretty comparable to MIPS.

A zero register already existed in some computers with vacuum tubes, almost 70 years ago, this is not a new idea that can be attributed to MIPS or RISC.

It is a good feature, which can reduce substantially the number of instructions that must be implemented, because many single-operand operations are just special cases of double-operand operations with one null operand.

This is why it was used in many early computers, which had to be simple due to the limitations of their technology, and then it was used again in most RISC CPUs, which have been simplified intentionally (and not only in MIPS; among the more successful RISC ISAs also IBM POWER has it; only 32-bit ARM does not have it, due to its unusually low number of general-purpose registers, in comparison with the other RISC ISAs).

Thanks!

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