LightPC: A Resilient System Using Only Non-Volatile Memory | Hacker News Reader

LightPC: A Resilient System Using Only Non-Volatile Memory

news.kaist.ac.kr

This is really clever, but it seems "obvious" in the sense that it must have been attempted before, right?

> LightPC matches the performance of DRAM by minimizing the internal volatile memory components from non-volatile memory, exposing the non-volatile memory (PRAM) media to the host, and increasing parallelism to service on-the-fly requests as soon as possible.

If it really does match the performance of DRAM, then this seems huge. Surely it can't be true? Maybe it's only true for small amounts of memory?

There's plenty of previous work on NVM as main memory. This looks like an incremental improvement. All real NVM chips I'm aware of are slower than DRAM so the only way to match DRAM performance would be to use more chips which has packaging considerations.

NVM is mostly theoretical since XPoint is mediocre and nothing else is available.

HP had a much-hyped project called "The Machine" that centered around a massive amount of NVM, surrounded by processors:

https://newatlas.com/hewlett-packard-enterprise-the-machine-...

My prediction is that this tech will remain an unviable experiment. Until Apple just goes ahead and integrates it into the M3 chip at which point everyone on Hackernews will have to have one.

Are there no longer issues with regards to the limited number of writes on flash chips before they wear out ?

This is probably using the stuff Intel was putting in its Optane non-volatile RAM.

Downside is, turning it off and back on again doesn't fix anything.

I don't think this is about flash.

It would have sufficed to provide just enough battery or capacitor to copy from regular RAM to non-volatile storage in case of a power drop. For reliability, you just need to ensure stuff is charged up again, on startup, before resuming.

Half the point of NVM was to be cheaper than DRAM, not more expensive.

The point of NVM is to be NV. A few GB of DRAM for cache and a super-capacitor would not increase cost notably, but would eliminate any performance impact, and also give a more reliable recovery.

Issue: NVM endurance limits.

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