Here’s a paper describing a simulator that worked by similar means:
https://dl.acm.org/doi/10.1145/384265.291063
It’ll help, but still won’t get you down to the 10-20x cycle overhead range that you need to claim success.
https://dl.acm.org/doi/10.1145/384265.291063
It’ll help, but still won’t get you down to the 10-20x cycle overhead range that you need to claim success.
You a right, they get a 190-360x overhead, and on today's CPUs, I think I need need to get it down to about 20-30x overhead to get realtime on current CPUs. It's only off by a single order of magnitude.
Though, it would be fast enough for some usecases. 10% of realtime would be bearable for some TAS usecases.
It might be possible for me to improve on what they have. For starters, they aren't using a trace-based approach and I think they are applying the memorisation on every single branch, correctly predicted or not, and every single memory access (even when they hit L1). But I would need a 10x improvement over what they had, and that's a big ask.