Oh I should've read the whole article first...apparently reduced memory usage leads to longer battery life which is a worthy goal.
However, RAM remains one of the largest power consumers, and so reducing memory usage also reduces power usage, which improves battery life.
Tom's hardware has a great article on this here: http://www.tomshardware.com/reviews/lovo-ddr3-power,2650-2.h...
Note in particular the figures at the bottom of the article page.
On modern CPU's, HALF- or MORE of the silicon is used to afford 4-16MB L3 caches. A CPU die is not much smaller than a DRAM chip, and a 1GB chip of DRAM is less than $10 these days judging by the prices of 16GB, 16-chip sticks of DRAM.
- CPU caches are wired much more complex than SRAM memory modules would need to be. It may be shared between CPUs, and being n-way surely requires silicon, too.
- if the ratio is way more than 10, why, then, do I find zillions of references stating that a) DRAM needs a transistor per bit, and b) SRAM can be built with 6 transistors per bit?
The best possibility would be fully realising the NUMA architecture, and giving each core a stack of dedicated SRAM or DRAM at sizes of 1GB (these would have to be off-die though).