There are lots of reasons why some HDL could be unsynthesizable:

- multi-driven nets where two or more signals are driving the same node

- the target not supporting certain features like multi-clocked FFs

- missing components or libraries (not uncommon if you're trying to use VHDL 2008, for example)

- timing analysis failing, meaning the HDL isn't fast enough / the critical path is too long for how fast the fpga is going to go

And while not necessarily being unsynthesizable, a lot of tools like Vivado will heavily optimize the HDL, meaning if you forget to connect a part of the HDL to the output or do something with it, it will be removed from the design.