Guy expands 6502 to 16M address space by intercepting the databus and re-mapping unused opcodes and clever use of the spurious signals generated by the cpu when executing other undefined opcodes, adds a few registers to make the whole thing transparent from an assembler programmers point of view. In other words, there is no difference to the programmer between native and newly minted instructions.

On top of that he boosts the speed of his forth interpreter by concentrating on a frequently used construct called 'NEXT' in a way that should make anybody that has tried to optimize the inner loop of some VM or language proud. After all, what better way to optimize in such a situation than to be able to mold the instruction set to your desire.

He then uses this home-brew Frankenstein contraption as his benchtop computer for multiple years to do real work (instead of just shooting some pretty pictures and calling it a day).

hth

The most significant part (I think, probably wrong) is on page 5[0] where he details the invalid instructions that do more than a NOP and why they're useful.

[0] : http://www.laughtonelectronics.com/arcana/BrideOfSonPg5.html

Sorry about the TLDR situation; it's on my list to revise the article by prepending an abstract. BTW suggestions and questions about the article are welcome.

@mjhall - you're quite right; the strange, phantom 65c02 operations dramatically expanded what I could do with this project. It's extremely cooperative of the CPU to generate a memory address while leaving all registers unchanged! Although it's true I could've used the PROM to map NOPs onto CMP or BIT instructions and gotten my addresses that way, that approach preserves the registers but still stomps the Flags. In contrast, the "LDD" operations are ideal for the job -- an opportunity handed to me on a silver platter!

-- Jeff