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Comment by pphysch | Hacker News Reader

> This enables M1 Ultra to behave and be recognized by software as one chip, so developers don’t need to rewrite code to take advantage of its performance. There’s never been anything like it.

Since when did the average developer care about how many sockets a mobo has...?

Surely you still have to carefully pin processes and reason about memory access patterns if you want maximum performance.

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Not sure what is required of a dev, but as an example, Adobe Premiere pro doesn't take any advantage of >1 CPU, at least on Windows. https://www.pugetsystems.com/labs/articles/Should-you-use-a-...

It’s probably not “average developer” either but some of the big box software still has per-socket licensing, or had until recently anyway.

Article is 5 years old.

CPU as in core or socket? These days most CPUs are "many-CPU-cores-in-1-socket" and having X CPU cores over 1 or 2 sockets make a small difference, but software does not care about sockets.

Plenty of enterprise software is licensed on a per-socket basis.

And if they read this press release they will probably try to switch to per-core licensing.

I thought that to extract peak performance out of NUMA based systems, you had to get down-and-dirty with memory access & locality to ensure you don’t cross sockets for data thats stored in RAM attached to other CPUs.

Or am I out of date on NUMA systems?

This is what they were referring to. To get optimum performance out of NUMA systems, you need to be careful about memory allocation and usage to maximize the proportion of your accesses that are local to the NUMA domain where the code is running. Apple's answer here is essentially "we made the link between NUMA domains have such high bandwidth, you don't even have to think about this."

The big dies these days (M1 included) have non-uniform memory access baked in because they distribute the memory caches. If you want maximum performance, you will certainly want to be aware of which "performance core" you're running in.

This line is nonsense and you can safely ignore it. There have been multi-chip-modules that act like a single socket for many years. In particular, pretty much every current AMD CPU works that way. I guarantee you that for the M1 Ultra, just like every CPU before it, the abstraction will be leaky. Programmers will still care about the interconnect when eking out the last few percent of performance.

Remember the Pentium D? Unfortunately, I used to own one.

The existing AMD CPUs aren't quite like that. Technically they are all UMA, not NUMA - the L3 cache is distributed, but they are all behind a single memory controller with consistent latencies to all cores. But the Threadripper 1st gen was absolutely like that. Straight up 2+ CPUs connected via infinity fabric pretending to be a single CPU. So is that 56 core Xeon that Intel was bragging about for a while there until the 64 core Epycs & Threadrippers embarrassed the hell out of it.

>Technically they are all UMA, not NUMA - the L3 cache is distributed, but they are all behind a single memory controller with consistent latencies to all cores.

This stuff rapidly starts to make my head spin. I have not studied interconnects and have never written any NUMA-aware software. I will just post this link (read the "Memory Latency" section):

https://www.anandtech.com/show/16529/amd-epyc-milan-review/4

As I understand it, the I/O die is partitioned into four quadrants. Each quadrant has two memory controllers and is attached to two compute dies. CPUs can access memory attached to the same quadrant with lower latency than going to another quadrant. This is a NUMA system that can be configured to appear as one logical NUMA node.

I believe their smaller parts with two or fewer compute dies will be UMA, but with the same non-uniform latency to L3.

>So is that 56 core Xeon that Intel was bragging about for a while there until the 64 core Epycs & Threadrippers embarrassed the hell out of it.

I believe the 64-core Epycs and Threadrippers came first. The 56-core Xeon was a purpose-built part for HPC, so it wasn't quite a marketing gimmick.

They are referring to the GPU part of the chip. There are two separate GPU complexes on the die but from the software point of view, it is a single large GPU.

For any applications people use to justify buying a more than one socket machine needs this.

Eg simulation softwares often used in the industry (but the one I’ve on top of my head is Windows only.)

Anyway, the point the make is this: if you claim doubling performance, but only the selected few softwares as you observed would be optimized to take advantage of this extra performance, then this is mostly useless to the average consumer. So their point is made exactly with your observation in mind, that all your softwares is benefiting from it.

But actually their statement is obviously wrong for people in the business—this is still NUMA and your software should be NUMA aware to be really squeezing the last bit of performance. It just degrades more gracefully to non optimized code.

I think its more the case that OSX hasn't really had SMP/numa for a long time.

My understanding was the the dustbin was designed with one big processor because SMP/numa was a massive pain in the arse for the kernel devs at the time so it was easier to just drop it and not worry.

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