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Comment by blippage | Hacker News Reader

I follow some of the writings of Nassim Taleb. I came to the conclusion that RISC-V will "succeed" because there's no way for it to fail. It's like Linux.

I don't think licensing fees to ARM are a problem per se, it's the "frictional costs" that it introduces. My understanding is that the Raspberry Pi developed their RP2040 because ARM had a reasonable package available for its low-end Cortex-M processors, which doesn't apply to their higher-end Cortex ones.

RISC-V doesn't even have these restrictions. Even extremely small outfits can play around with RISC-V designs. Most of them won't go very far, but with enough lottery tickets, one of them is bound to draw the winning numbers.

Sure there are considerable obstacles. I toy with microcontrollers. For hobbyists like me, ARM processors are still the most sensible choice. I'm not expecting any shift from that for at least five years. But who knows after that? Anything can happen.

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ARM's less open platform also comes with some advantages though. It's easier for ARM to prevent ecosystem fragmentation and non-standard instruction set extensions. Or to push for migrating to newer platforms like the move to 64bit ARM.

Software is less affected by these issues because it's inherently more flexible. If I install some wonky experimental Linux feature, it doesn't really matter and I can just revert. Different story when this is baked into hardware. The startup costs for independents to contribute to a software only ecosystem is also much lower. How many organisations have the talent to contribute to RISC-V, but wouldn't be able to afford purchasing a license?

Didn't mean to sound so negative but I worry in the hardware space that the advantages of such an open design are not as great.

That's the equivalent of saying forking is bad.

The big plus of RISC-V is allowing those who accept the risks and cost to experiment and develop new specialized components. Arm won't let you.

> ARM's less open platform also comes with some advantages though. It's easier for ARM to prevent ecosystem fragmentation and non-standard instruction set extensions.

It's kind of funny way of looking at the core part of the ARM ecosystem while forgetting how much outside of the CPU is non-standard, undefined. None of the ARM devices share bootloader, device enumeration, and a plethora of things needed for an open, non-fragmented OS/Software ecosystem like how PC does.

Maybe you can run parts of the same ARM machine code on most devices, but it's not terribly portable to be honest, it has to be very generic. For example, Android devices end up in a pile of trash because you can't just upgrade the kernel to the latest version on a 1, 5, 10 year old smartphone without losing functionality or being stuck at step 1 for the lack of tools from broken forum links and shady fileshares. So much for software flexibility...

So you're criticising Arm fragmentation but the possibility of more fragmentation in RISC-V is ok?

My idea is that a CPU is just a component and it's useless by itself without considering the rest of the computer system. ARM needs to dip more into standardising the rest of the picture, and the RISC-V guys could also start looking into creating an open computer architecture initiative/group to prevent further fragmentation.

Agree 100% - Arm could certainly do better.

I do worry though that the RISC-V ecosystem could be really torn in two by a big player (Intel?) who adds proprietary extensions and associated software.

RISC-V is trying to create a standard platform specification to address some of these concerns

https://www.youtube.com/watch?v=l2w4cWFpqAA

So ARM's lack of fragmentation means I can install any Android ROM on any ol' ARM device?

Or are ARM devices so crazily fragmented that I need to custom compile for each and every device in existence?

The market is already fragmented depending on how you look at it. There are lots of custom chips for all sorts of stuff today which has their own ISA because ARM cannot be used because it imposes the requirement to implement around 1000 instructions.

With RISC-V you could end up with LESS fragmentation, no more. A lot more of the specialized chips can start using RISC-V with particular extensions rather than inventing their own ISA.

That has benefits in that one can reuse more tools and code.

I don't see a reason why RISC-V for desktop systems or high-end smart phones should get any more fragmented than ARM. There is already a standard set of extensions RV32G for these kinds of hardware.

And at least RISC-V has been designed from scratch to handle fragmentation. The base standard gives developers a way to check what extensions are supported in code. It also allows operating systems to include code to simulate unsupported instructions.

RISC-V is prepared for fragmentation in a way that ARM isn't. It is different to design for that possibility and find ways to deal with it as opposed to design around that idea that through strict rules one would avoid fragmentation ever happening.

If anything was standardized, Linux wouldn't have the drivers problem.

> will "succeed" because there's no way for it to fail. It's like Linux.

Didn't OpenRISC fail? https://en.wikipedia.org/wiki/OpenRISC

Also there are different definitions of "succeed" from different viewpoints. In academia RISC-V is already a big success.

Good point. How is RISC-V better than OpenRISC's ISA?

Mainline Linux kernel support is a fairly big plus.

RISC-V does not have unused/unusable exceptions and tries not to expose internal details of implementation as much as possible.

To show difference, OpenRISC has division-by-zero exception which is unnecessary - it can be ruled out by compiler or, if compiler did not rule it out, can be checked and triggered by comparison, conditional jump and special trap command. MIPS did exactly that almost fourty years ago.

OpenRISC also has (optional) branch delay slot, which complicates out-of-order implementations and even in-order implementations with memory mapping unit - what state should you keep to properly handle MMU exception in the branch delay slot command?

Alpha AXP, being the ISA that was designed to be useful for 20-25 years, ditched both of these in early 1990-th. RISC-V, which extends experience of RISC-IV (SPUR [1]) and other RISC designs, including POWER and SPARC, also does not sport these atrocities.

[1] https://news.ycombinator.com/item?id=19266152

All in all, RISC-V represents an ISA that can be implemented differently with less effort than OpenRISC and, to be frank, most other RISC ISAs.

They did not build on OpenRISC because it was originally mostly just a chip and it was 32 bit only.

RISC-V started out with the goal of being capable of very small to really large chips and do 32 and 64 bit.

OpenRISC did add 64 bit later but by that point RISC-V was already going.

> I toy with microcontrollers. For hobbyists like me, ARM processors are still the most sensible choice. I'm not expecting any shift from that for at least five years.

I started using ESP32C3s in my projects. They are cheap powerful RISC-V micros supported by Arduino SDK. IMHO it's already better than the ARM offerings, but I'm still waiting for good Rust support.

The ESP32C3 seem to have the same friction - closed wifi blobs? They might get supplanted by something with a more malleable software stack.

someone told me the wifi blobs exist because of regulations prohibiting wifi chipsets from being easily modified to use illegal frequencies, but they still want to do much of the functionality in firmware so they can have more flexible asic designs that can keep up with standard changes. If that is all true, wifi blobs are unlikely to change.

Regulatory issues are one reason. The second is that the wifi side of things might be some 3rd party IP they bought and the licencing terms prevent open sourcing it. Wifi stacks are complex and filled with edgecases. And every release just makes that moat bigger.

... . -. -.. / -- . / .- -. / . -- .- .. .-.. break .. / .... .- ...- . / .-.. --- --- -.- . -.. / ..-. --- .-. / -.-- --- ..- break 6c6f6d65696e30313031676d61696c636f6d

Are there any bigger RISC-V boards around yet? I'd love to goof around making a toy RISC-V operating system, but those ESP32C3s look a bit gutless (400kb of RAM? Oof.).

Ideally I'd like something specced closer to a raspberry pi.

What 400kb of RAM on an MCU?! That's a huge amount for an MCU. Arduino's started out with 2kB of SRAM. Linux also requires a MMU to run, which most's MCU's don't have.

Thanks; but I don’t want an MCU. I don’t even know what an MCU is. Arduino style devices aren’t interesting to me.

I want something I can run Linux, like a raspberry pi but RISC-V. I know there were some bigger development boards out there for $600+ a few years back. Is there anything in the pipes which is smaller, for hobbyist messing around?

There is at least one now called the Sipeed Nezha, costs about $115 on Aliexpress with 1GB RAM. Seems like it's similar to an older RPi.

Oh thanks for pointing me in the right direction. It looks like they're now shipping $20 development boards with their new chips in the Sipeed LicheeRV. 512MB of ram and linux support:

https://www.aliexpress.com/item/1005003594875290.html

The HiFive Unmatched[0] from SiFive is a beast of a dev board, but with a price to match ($665 from Mouser). For a smaller Arduino-style board, the HiFive1 Rev B[1] exists as well, but it's more an MCU than CPU.

[0]: https://www.sifive.com/boards/hifive-unmatched

[1]: https://www.sifive.com/boards/hifive1-rev-b

> It's like Linux.

It's unlike Linux in so many ways, licensing being just one really key example.

RISC-V may well succeed but not because it's like Linux.

Indeed - it's not like linux. It's an ISA spec, not an implemention.

It's more like POSIX or something from that comparison.

If you are making a custom chip, you will still license a ton of different IP blocks that you will pay licensing costs for. What is special about the CPU?

I guess it's nice to have a free CPU core but at the end of the day you want USB, external RAM, a bus to connect all these things and so on.

Maybe we will have free implementations of those at some point but it probably won't be from the current crop of chip designers - there have probably never been more ungrateful, non-reciprocal users of free software.

Right. When you are talking cores, this is all fine. A completely valid topic for academic discussion.

When you are talking chips with peripherals and packages and memory configs, it gets a little more muddy.

When the conversation moves from academic to trying to buy a chip and ship a product.

I am aware of a popular chip vendor next year making a three core chip. Core0 the fastest and primary is a RISCV, it will be flanked by two smaller and weaker ARM cortex m0 or m4s.

They’re doing that because they have peripherals established for the ARM and almost none for the RISCV.

RISC V cores are not necessarily free.

I am also a hobbyist and that is actually what makes me very hopeful about RISC-V. For a non-expert like like RISC-V instruction set is actually possible to grasp. Modern ARM is getting way too complex.

Depends on what you do. If you just write code in C/C++, then it doesn't matter. But if you actually like to dabble with assembly code then RISC-V actually makes that possible.

It may not be as awesome to write as 68k was back in the Amiga days, but RISC-V is the closest to that which I have experienced in modern times.

In particular I think RISC-V has a great potential in teaching a new generation how programming works in detail. I felt when I went into this industry that it helped being able to actually read the low level code produced by the compiler and understand it. That is getting ever more difficult.

We are reaching levels of complexity where it becomes very hard to give anyway today the kind of bottom up understanding of how computers work that you could get back in the 80s and 90s.

Which part of modern ARM do you feel is getting too complex? And what is there to gain by making an ISA more understandable to humans? Educational ISAs already exist for learning. The complexity of even something like x86 is not a real obstacle for people who actually need to interact with it.

It is already possible to experiment with Arm IP for free with Arm flexible access.

Can you expand on Taleb's message, and what you mean when you say "can't fail"?

Free stuff does fail for all kinds of reasons.

Companies fail. Information doesn't.

By virtue of being open source, RISC-V won't vanish, no matter how many companies choose to adopt it as their ISA and fail.

Seems like, given enough time, one of those companies will just not die, and end up getting big.

There's a lot of open source projects, most of them fail. I don't think the availability of an OSS ISA is good enough to overcome the friction of adopting a brand new technology, unless it enables something that competitors don't. And it doesn't seem to do that w.r.t ARM (so far).

If I write a free operating system, nobody will use it except me. When I lose interest literally zero people will care that it exists. Hard for me to see how that would be a success no matter how many copies of the useless bits reside around the world.

You absolutely will (almost certainly).

But if you take the set of people who have written free operating systems, there's at least one big winner.

I can't remember the exact criteria that Taleb mentioned that led me to believe that great things might come of RISC-V.

So I'll fall back on the "optionality" argument. Vendors, particularly small vendors, can experiment with RISC-V either free, or very cheaply more so than they can with ARM. Right there, RISC-V opens up a segment that didn't exist before. They'll be more experimentation. When your downsides are limited, but your upside is potentially huge, that's what I mean by "optionality". This is a powerful driver of success.

Naturally, any individual endeavour can fail, but collectively, there's going to be some huge winners.

My prediction is that RISC-V will open up some new category of computing. I can't tell you what it is, who will do it, or when they'll do it, because I don't know. My point is not so much that I can predict what it will be, but merely that there are forces in favour of RISC-V.

I am not, however, predicting the imminent demise of ARM.

I think also that a lot of commentators are viewing things through the lens of what we understand and the received wisdom today. Even - or maybe especially - experts tend to be hemmed in by what is "obvious".

RISC-V is like a genie that's been let out of the bottle. You can't put it back in.

The "minion cores"[1] idea from lowrisc.org might be a good early example. You can find something similar for one ARM chip I know of (TI Sitara with PRUs), but only one that I know of...perhaps because it's expensive to experiment like that, as you mention.

[1] https://lowrisc.org/docs/memo-2014-001-tagged-memory-and-min...

Vendors can experiment with Arm for free with “Arm Flexible Access”!

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