It's really convenient to pass around pointers to a single GPIO pin on embedded systems that have a special region of memory where each byte corresponds to one pin rather than the usual 8. Atomic access to bits would also be convenient.
We have atomic bitwise operations already (look at glibc's mutex implementation), and the unit atomic operations work on is a 64-byte cache line. Cache lines are useful because reading 64 bytes isn't really more expensive but it improves sequential memory access by a lot.