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Comment by snvzz | Hacker News Reader

Required or not, it is desirable.

Looks like this has been put together by Efabless themselves. I dont think the rtl would be too different from OpenFPGA(https://github.com/lnis-uofu/OpenFPGA) married to the caravel f/w.

My guess would be that the first prototype that they made was too buggy to publish. The promise is that they will share the final design, and I am fine with that.

(I am not affiliated with the project, but backed it)

Update: marcan_42 apparently found it: https://efabless.com/projects/33

I don't think they are the same:

Look at the picture in it versus in the link:

https://groupgets-files.s3.amazonaws.com/Efabless/open-sourc...

They are different. Also, if you go to https://vlsicad.ucsd.edu/Publications/Conferences/383/c383.p...

Figure 6: You can find the image from the link (top left), and the on ehtat you linked (bottom left), so they are two different projects.

According to this website: MPW-1 had a hold time violation in it's clock tree, so the RISC-V is unusable.

https://www.zerotoasiccourse.com/post/mpw1-bringup/

Yikes. If I'm understanding that correctly every chip that came back from MPW-1 was more or less unusable - they were all required to gate access to I/Os behind the same management processor provided by the company organising the run, and because that management processor was broken they couldn't configure the I/Os to route through to their own designs.

Yeah that is my understanding too. You REALLY don't want a hold time violation, as you have to go in and edit the chip circuitry to fix that.

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