My interesting battle story around this is that I first implemented the MDIO as bit banging in the kernel. This used quite a bit of CPU, which I wanted to use for other things. I switched it over to the PRU and CPU usage dropped to 1%. Great! But the data rate was much slower, with huge latency spikes. It turned out that the CPU usage was so low that the CPU governor thought the system was idle, so was throttling the CPU to just a few hundred MHz. I had to change the governor to keep the CPU clock to 100%, then everything was about 10x faster.
> OUT EXEC allows instructions to be included inline in the FIFO datastream. The OUT itself executes on one cycle, and the instruction from the OSR is executed on the next cycle. There are no restrictions on the types of instructions which can be executed by this mechanism. Delay cycles on the initial OUT are ignored, but the executee may insert delay cycles as normal.
If your PHY’s data sheet says clause 45 register access only and you don’t have GPIO access as the bus master, run away.
Unfortunately I was tasked with emulating a clause 45 PHY on a clause 22 bus. Without creative use of the microcontroller peripherals, it is next to impossible to achieve implemented a 2.5Mhz slave.
I had to use an edge interrupt to jump in to a while loop state machine, whose state was determined by a timer counter driven by the MDIO bus, with all GPIO acessd via hard coded bit banded GPIO.
Fun times, but this is definitely an FPGA job.
You could compare this to a GPU (special purpose coprocessor for vector calculation) or a very complicated IO peripheral you are configuring.
An FPGA allows you to build up actual hardware gates and wire them together. For pio you configure existing hardware.
There are some similarities in the domain you're using them, though. FPGA are often used for timing critical IO as well.
The real shame of modern microcontrollers is the decoupling of peripherals and GPIO from the main processor. It prevents these sorts of hacks as all access has to be through the memory bus, effectively capping bitbanging at sub 10MHz speeds.
Could you clarify that? It was my understanding that the PRUs of the TI AM355x Sitara specify execution time true to the cycle.
Every GPIO implementation I’ve seen on modern processors accesses it via a memory mapped peripheral. The difference being accessing a memory bus is not a single cycle operation. You have to wait for the bus to be free, then wait to fetch or write the data.
The most extreme analogous example of this is modern cpus are effectively infinitely fast but bounded by cache misses that necessitate memory access.
This is fundamentally why every toggle a GPIO pin benchmark is flawed. What is really being measured is memory bus latency.
This misunderstanding is why people have trouble reconciling why a multi ghz processor cannot also bitbang GPIO at ghz speeds, although if such a processor existed it would be amazing.