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Comment by javajosh | Hacker News Reader

>By focusing on the only architecture type in mainstream use on the market today, namely island-based (also called tile-based) FPGAs, the standard reaches a level of universality and conciseness, which makes it easy to work with, adopt, and implement.

This implies that there are other architectures this group looked at and felt did not need to be addressed in this announcement. What are they, I wonder?

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The other popular architecture is the CPLD (complex programmable logic device) which grew out of the PALs (programmable array logic) of the late 1970s. Altera pioneered the CPLD and Xilinx the FPGA in the mid 1980s.

Until recently "FPGA" was used for tile based architectures and "CPLD" for macroblock architectures, but marketing has redefined the terms such that small FPGAs are now called CPLDs if they are non volatile (they are already configured when you turn them on).

I think it might be trying to explain the difference between a format for use when building ASICs and one that targets fpga architecture. With an fpga, there is a structure (the tile) that contains some ram some, luts and other blocks. The luts are reconfigurable, and so is the wiring, but otherwise the fpga is mostly fixed. So this is quite different than an asic, where there are more cell types (flip flops, logic gates, or fets, etc) and they can be freely placed in the design.

Pretty sure it’s just PR/HR gibberish to justify why this project is so acutely aware of the Xilinx chips they’re supporting.

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