HDLs like VHDL and Verilog are at a different level. If HDLs are like C, the interchange format is more comparable to a .o file.
That being said, EDIF already exists.
That being said, EDIF already exists.
My crowning glory hack from that era was a perl script that read verilog netlists and lisp placement data between the place and route stages of the P&R tool and did location dependent scan insertion producing a netlist and a the lisp instructions to the P&R tool to fix it up
EDIF is big and complex and there are different only partially compatible versions in parallel use.