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TowerTall

>SpaceX - Starlink (AS14593) has added 2x100G bringing their capacity to a total of 2x2x100G

Why not 4x100G?

>Welcome Apple Inc. (AS714) at 2x1x100G.

Why not 2x100G?

>Akamai Technologies, Inc. (AS20940) has added 3x100G bringing their capacity to a total of 3x100G and 2x100G

And why not 5x100G.

How does one read these numbers?

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As another said it is referring to LAG (Link Aggregation Groups or "EtherChannel").

From a logical construct perspective each "2x100G" interface is represented by a single "200Gbps" layer 3 interface. When referring to 2x2x100G, it really is meaning 2 layer 3 interfaces, consisting each of 2x100G ethernet interfaces in the link aggregation group.

Hashing of L3/L4 header data provides for consistent flow -> lag member mapping to avoid OOOs and other historical multi-link issues.

These are all likely LAG-style circuits, bonding multiple physical circuits into a single circuit. This increases the overall bandwidth available without increasing management and routing overhead needlessly, as individual circuits may do.

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