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Comment by geenew | Hacker News Reader

Couldn't find much info on the process size in the Reuters article, but the Intel press release[0] says this:

" “The Ohio factories are designed for the ‘Angstrom era,’ with support for Intel’s most advanced process technologies, including Intel 18A."

This[1] doesn't give a transistor density for 18A, but the 20A transistor density is greater than the TMSC 3nm, fwiw.

[0] https://www.intel.com/content/www/us/en/newsroom/news/intel-... [1] https://www.anandtech.com/show/16823/intel-accelerated-offen...

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18A is consider as 1.8nm in TSMC terms.

1 Å = 0.1 nm, which is roughly the diameter of a hydrogen atom.

This mandatory comment is your threadly reminder that node names are entirely unrelated to any physical dimensions, as has been the case for many years now.

You should not interpret node names as meaning anything more than a point on the semiconductor roadmap. Nodes that share the same names across foundries will not have the same performance characteristics, but are usually roughly comparable (especially since Intel's new naming scheme).

> node names are entirely unrelated to any physical dimensions

I agree they're not necessarily related to any particular transistor dimension but are you sure it's entirely unrelated to any physical dimensions? If so, here is a question I have. 28nm, 22nm, 20nm, 14nm, 10nm, 7nm, 5nm, 3nm. What progression is that? Why skip 6nm and 4nm?

A "full node" step is 1/2 the area of the previous. Since area is dimension-squared, 28 x 28 == ~800 area, while 20 x 20 == ~400 area.

So 28 -> 20 is a "full node" decrease (ie: twice the transistors).

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We can see the full-node step from 14nm -> 10nm as well: 14 x 14 == ~200, 10x10 == 100. So its a full node step. The next full-node is 7 x 7 == ~50, which is half of 100. After 7 comes 5, because 25 is half of 50.

The next full node is sqrt(12.5) or 3.5, smack dab between 3 and 4, so not really easy to round.

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The steps in between are "half-node" decrements, where you didn't quite achieve a full 1/2 area reduction. An incremental technology that represents something in between the full node step progression.

That's an interesting explanation and somehow I never heard it explained that way before. It makes sense if one thinks of the transistor count doubling relative to where that company previously was, and not where the industry is. In the transistor density plot each curve is roughly x^2, but with different initial conditions.

https://www.techcenturion.com/7nm-10nm-14nm-fabrication

2^x, not x^2.

x^2 is 1, 4, 9, 16, 25.

2^x is 1, 2, 4, 8, 16, 32

Well, there's always a distance between SOMETHING that each company can point to, it's just those things are constantly changing.

Somewhat related- this reminds me of this recent fact that I learned [1] that 1" camera sensors are not 1" in any dimension whatsoever. That number is rooted in historical diameter of a tube that video camera "sensors" were housed in. That tube was 1" in diameter.

[1] https://youtu.be/-njHjebtIg4?t=495

CRT monitors and TVs were the same: the advertised size was the size of the picture tube, not of the visible area.

Definitely not entirely unrelated.

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