Comment by iambvk | Hacker News Reader

Comment by iambvk | Hacker News Reader

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Instead of Read-Modify-Write, I like to think of it as Read/Determine/Write cycle.

A note worthy point is that, Paxos actually expects proposers to drop their value and carry-forward someone-else's value to complete the consensus. This is typically not an intended behavior from client's point of view, but proposers role is to form the consensus, not push their value.

Read phase is basically understanding if there is any value that could've been chosen when F nodes are unavailable.

Determine phase is to choose to carry-forward any value (if-any) from the Read phase or use the new value from the client.

Write phase is to actually ask majority of the acceptors to save the value selected in the Determine phase.

You are totally correct that in Paxos the proposer is supposed to "carry-forward" the value proposed by somebody else. In this view, which is how everybody understands Paxos, Paxos is an algorithm for consensus.

However, the proposer can also modify the value proposed by somebody else, and it turns out that this is a perfectly valid algorithm for implementing a distributed read-modify-write. This variant does more than just consensus---it basically behaves like a fault-tolerant memory with an atomic update operation (think compare-and-swap or load-linked/store-conditional). In his blog post, GP also mentions that paxos is a read-modify-write transaction, but perhaps I read too much into what he is saying. Either way, this RMW variant is correct, I have verified it exhaustively with TLA+, and it is used in a few production systems that I have implemented.

The difficulty is now to say exactly what this RMW variant does. I was hoping that GP (or anybody else) may have some insights.

In case anyone wants to read more about the RMW variant, this is called CASPaxos: https://arxiv.org/abs/1802.07000

I first learned about this as a project called gryadka and I had trouble believing that extending Paxos from consensus (write once) to a full linearizable register worked until model checking a TLA+ spec for it that I wrote.

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