Breakthrough: The Secret to Making Processors 1,000 Times Faster | Hacker News Reader

Breakthrough: The Secret to Making Processors 1,000 Times Faster

mashable.com

119 pointsmanyad94 comments

This is a poorly written, sensationalistic article. Here's the original press release:

http://www-03.ibm.com/press/us/en/pressrelease/35358.wss

Basically, this is about IBM and 3M starting a new research project. Whether it would work, how long it would take, at what cost - these are all open questions.

I think you just described 90% of the content on Mashable.

There is a lot of sensationalist PR from IBM. The Cat Brain, the Smarter Planet thing, the AI processor and now a 1k times faster processor..... some arbitrary stuff an nothing concrete. I wonder what this PR strategy should accomplish and who is the target for this.

> I wonder what this PR strategy should accomplish and who is the target for this.

'No one ever got fired for buying IBM.'

I noticed this too. My theory is it's brand image-building to differentiate their enterprise offerings from say, Accenture or Deloitte. Most of their revenue currently comes from enterprise software and hardware. To a 50-year-old C[EI]O who doesn't look too deeply into tech any more, I'm sure this feels like a nice throwback to their innovations in the past few decades.

Let me get this straight. Today, we have trouble dissapating the heat produced by a single die.

To solve this problem, we are going to stack 1000 dies, and produce 1000x as much heat.

Who cares about whether the heat can travel up the column- where is the improvement in cooling technology to remove 1000x the heat from the die stack?

The point with 3d layout is that you can have shorter interconnects, which means far less resistive heating, and less junction loss. It also means that your path lengths can be shortened, possibly allowing you to bump up the frequency.

Stacking stuff means you should be able to run cooler for the same amount of processing power.

1000x? I think that's probably BS. But I can see this being a significant win.

How about L1 cache (or even just L3 cache) measured in gigabytes? That won't increase the execution speed of individual instructions, but your effective processing power would increase dramatically.

The problem is that as cache size gets bigger, the associative memory lookup gets slower. There's a tradeoff.

What? Why is this, isn't memory indexed for direct access?

We're talking about cache, where the addresses of blocks in cache do not have a 1:1 mapping with addresses in memory.

Read the section on associativity: http://en.wikipedia.org/wiki/CPU_cache

You get to choose your associativity, you could build a direct-mapped 1GB L1 cache if you wanted. More fundamentally, a memory's access time grows with its capacity because the average and worst-case distances from a bitcell to the read/write port are longer.

If you pack enough memory in the same package and connect it to the CPU through a bus that's fast enough, on-chip memory that used to be used for caches can get promoted to main memory and off-chip RAM becomes a fast cache for your SSDs and a way to synchronize context between different chip stacks.

Put the GPU and VRAM on the stack and all you need is a couple HDMI ports going out of the chip.

Cache is already about as fast as you can get without significant compromises in size. L1 cache runs at speeds fast enough that increasing the size (and average seek time), or increasing the distance the signal has to travel, will decrease access times significantly. So it doesn't become about how 'fast' the bus is, or how much memory you can pack on.

Putting a good chunk of memory between the processor and the external memory bus would allow interconnection through a much faster bus than the external one, reducing the penalty of a cache miss.

The two of you are arguing about different things. You are arguing the point of increasing cache to reduce misses. The other guy is arguing that increasing cache size will degrade cache performance as a unit. These are distinct arguments.

This makes me think of an interesting question- the back side of a die is raw silicon. How do you stack die and still interconnect? Do you sink metal through the bottom of the wafer?

Yes, through-silicon vias are metal-plated holes that go clear through the wafer ( http://en.wikipedia.org/wiki/Through-silicon_via ).

IBM talks about up to 100 layers, not 1000. Not all components have the same power requirements or are even powered up at the same time.

Also this is IBM research. They don't need to make robust processors for the consumer market. If the CPU requires watercooling or better, IBM can do and sell that. They already have such solutions for super computers and mainframes in the field.

I would assume the heat would be expected to ooze out the sides of each layer... e.g like the condiments leaking out the burger when you squeeze it :-)

Actually, this makes me think. The area now dissipating heat is much smaller (perimeter of the square * h, and used to be the area of the square). You have to dissipate the heat. The solution really can't be as simple as the article proposes.

First 3D silicon stack I saw was in the late 80s. (Back then it was a stack of 2.) The field has produced a rich string of PR announcements and funding proposals over that time though.

The problems then as now: Heat dissipation and signal integrity as you pass through the stack.

3D game programming in pure Python, anyone? :)

If this is real (and since it's IBM and they're claiming production by 2013, I'm optimistic), this is going to be a huge game changer on so many levels.

This does not look like a big win for Python, since it's most likely to provide you with ludicrous amount of computing cores, and Python currently is a bad tool for concurrent computing.

Yes, but because of what they'll be able to write in C++ :) (And in Python you'll be able to write Call of Duty)

Pixar movies quality rendering in game play with C++ maybe.

If we're going to increase processing power by stacking instead of shrinking, then we will double the volume every 18 months. We'll be back at room-sized computers in 40 years :-)

This is really exciting. I don't see anything with this techology that would limit it to just CPU chips. I'd imagine it would work just as well in a GPU chip. That would make incredibly realistic simulation of graphics and physics possible.

It would obiviously revolutionize gaming completely, but most imporantly it would revolutize science. Imagine having the power of the whole Folding@Home network in your laptop! Imagine how much power the future Folding@Home projects and other similar projects will have.

I'm a diehard optimist, but a sudden 100-1000x increase in ordinary CPU speeds could have the possibility to save thousands (if not millions) of lives and advice science a hell of a lot!

The glue helps with heat dissipation, that heat came from using electricity. 10'000 systems stacked on top of each other would consume 1MW assuming each one would consume 100W of power at full usage.

What life saving things are currently CPU bound?

so, asking questions now results in downvotes?

> What life saving things are currently CPU bound?

Drug research, gene mapping, climate modeling...

Research.

Does anyone know by what metric it will be 1,000 faster? It seems like a technique for having massive numbers of cores in parallel, but I'm not sure how the adhesive would address any specific improvements to the cores themselves.

That said, even if it's just a way to get 1,000-core CPUs or whatever, it sounds like a remarkable breakthrough.

A lot of wait states in a CPU come from accessing memory outside of cache. If you make all the RAM in your system the same as cache, you'd get a huge leap.

If RAM clocked higher and pushed closer to a processing cpu would make everything 50 times faster it'd still need 20 times as much silicon. Considering ideal heat dissipation such a system would still need let's say 20x100w = 2kW of input power. Which is about what a fast boiling kettle needs. How much realistic is that?

Where do you get the 20 times as much silicon number? For example, SRAM typically uses 6 transistors per bit, as opposed to 1 transistor for DRAM. What are the other 14 transistors doing?

Yeah, that's an obvious one. Not sure how I overlooked that. Thanks.

I'm speculating wildly here, but I suspect a major benefit to going 3D like this will be improved chip layout -- no need to take a lengthy route around all the stuff in the middle just to get from the ALU to the L1 cache (for example), just go straight up.

Of course the article doesn't mention if it's possible to make (and align) vias through this special glue, but I would really hope so.

Bzzzzzt! And thank you for playing.

I miss Jim Gray, he really did see things clearly. His response to the Alpha processor was that some day a computer would be a smoking hot, hairy golf ball. The reasoning was straight forward, spheres have the shortest paths between any two points, as density increased you needed more and more connections (wires) which were getting finer and finer in diameter, and power dissipation, well it wasn't going anywhere as electrons moving around bump into things, get over it.

My speculation is that the future is carbon for a variety of reasons. In its many forms it has all the properties you need to make chips, from diamond insulators to graphene conductors and nano-tube semiconductors. It can make light, it can trap light, it can conduct heat like there is no tomorrow. Truly, the day we can drop layers of carbon down and control the structure as it drops, think 'maker-bot with a molecular carbon extruder head that works at nanometer scale' its game on for truly mind blowing electronics.

Well 3d processors have always been out there as a research subject. The issue is heat when you crank it up. The stream processors (your GPU) gets around it by doing less work per core.

And so the heat dissipation seems to be the major point of this news. Will be interesting to see a more technical writeup or some published papers on this.

So this is a way of dissipating heat more efficiently, such that chips can be apparently be stacked on top of each other -- does that really help all that much for consumer (and especially mobile) stuff?

Seems like you're still generating the same total amount of heat, that needs venting from the machine. And still consuming the same amount of power.

I'm sure there's some value here, but it's not going to arise from just stacking up the same chips we use today.

When large advances in processing power become cost-effective and widespread, programming paradigms will change to take advantage of the fact. Cases in point: the Cell processor and modern PS3 games that really take advantage of it, CUDA on graphics cards and all the scientific computing that is starting to shift to it, and even multi-core and the renewed interest in multithreaded programming.

I don't see how stacking chips would do anything but make the heat dissipation problem much much worse. There is no magical "heat dissipating adhesive", only substances that conduct heat better or worse.

A conventional chip is a thin planar heating element attached with maximal surface area to its heat sink and we have great trouble keeping them cool now.

Heat generated internally a cubic object is more difficult to remove because the volume that is generating heat grows faster in proportion to the surface area available for removing it. I.e., the heat generation grows with the cube of the unit length and the surface only with the square).

The worst shape of all is spherical which has the highest possible ratio of volume to surface area.

Even if they managed to put heat sinks in contact with all six sides of this stack of dies, they could (at best) only remove six conventional chips' worth of heat.

Unless they have a way of circulating liquid coolant through that volume, stacking chips like that is only practical if they're almost completely off.

Sure there's value. The biggest obstacle to cranking up clock speed is heat dissipation. If we can get the heat away from the chip faster, we can increase the clock speed.

I still don't really see how it would help with heat dissipation overall. Most low power desktop CPUs seem to run at around 45W these days. If you stacked 10 of them, presumably you'd get somewhere around 450W. 100 of them would give you 4.5MW. First off, how do you get the electricity to power these, and secondly what do you do with the heat after it's left the CPU?

For servers, you face the same problem. It's already possible to get power and heat density that is more than what your typical datacenter can handle. If the density increased by even 10 times we would presumably need some serious advances in cooling to be able to handle all those servers.

100x45W = 4.5 kW, not megawatt. 4.5 kilowatt is the same order of magnitude of a dryer.

I thought it was about delivering the clock signal to the processor (before the next cycle) ?

As I understand you have to make circuits faster and smaller at the same time, so you still have time for clock distribution...

> still have time for clock distribution...

We are talking about pretty radical processor designs. Why not go asynchronous if we are talking about coordinating multiple layers of silicon?

Wouldn't a principle advantage of an actual, innovative 3D chip be better component distribution? That is, on average all the parts will be much closer to each other, than if they were arranged on a 2D surface.

From the images, it appears inter-chip connections run over the external borders. This increases the distances signals have to travel and limits the width of the buses. I am not familiar with the technical limits of building vertical buses connecting the various chips glued together, but I assume 1000+ bit wide buses would not be impossible, so, although limited, the limits seem pretty high. Optical interconnects may also be possible in such confined devices.

It will be interesting to watch. If real devices built with that technologies start showing in p and zSeries machines before 2015, we'll have some serious performance bump in high-end computers.

What would this mean for the global economy?

This could have quite an impact on CPU-bound cryptographic algorithms.

Probably not. Most modern ciphers have security bounds measured in solar systems worth of atom-sized supercomputers. Hardware-accelerated attacks on 1024 bit RSA keys (for which no real-world attacks are published) are predicated on custom silicon.

A massive, massive improvement in compute might hasten SHA-1's demise, but SHA-1 is already on life support today.

It is unlikely that even a huge unexpected leap in compute power would change the fundamentals of how things are encrypted today. Unless something like quantum pans out, you can expect us to still be using RSA (or more likely ECDSA and ECDH), AES (or something like one of the eSTREAM finalists), and HMAC-SHA3 for the foreseeable future.

The thing that will change what our crypto stack looks like will be a new discovery in cryptology, not a new way to build super-cheap, super-fast processors.

Or in other words, you're only going to get constant factor improvements in asymptotic run times with these chips.

Yep.

I'm not a cryptographer, but generally when we get to the point where we can envision how a sudden reduction in compute cost could threaten an algorithm or construction, that's when people start freaking out. That's where we're at with SHA1, but I don't know what other building block is in the same position.

The same as always, more "value", specialization and jobs created which means more money for the rich and less money for the poor.

Are you sure you're in the right place? If you believe making bigger levers for human minds is evil, this might not be the right community for you, since it's what most of us are trying to do on a daily basis.

I like the way you phrased that - levers for the human mind.

Maybe when we talk about the fight against poverty and unemployment, we should talk about it in terms of the type of levers we are making. Like high-frequency trading is a lever that only very smart, very educated people can actually use. But all humans no matter their intelligence or education possess a flexibility that would let them be productive (beyond what can be achieved with automation), given the right levers.

High-frequency trading looks to me much more like a bug of the system - or at least a undesirable side effect - than a lever for the human mind. Most innovations, though, fall in the lever category :)

Would you have leveled a similar criticism against farming during the agricultural revolution?

Eh, it would actually be more reasonable in that context. Dipping into wikipedia for a quick quote:

>The shift to agricultural food production supported a denser population, which in turn supported larger sedentary communities, the accumulation of goods and tools, and specialization in diverse forms of new labor. The development of larger societies led to the development of different means of decision making and to governmental organization. Food surpluses made possible the development of a social elite who were not otherwise engaged in agriculture, industry or commerce, but dominated their communities by other means and monopolized decision-making.

(Dr Catbox's comment, though, was just kinda mindless reactionism and had nothing to do with the original question.)

The article is not very technical, but I wanted to understand: Would this enable non-CPU core to be also glued?

I mean a single stack of say 12CPU layers, 12GPU layers, 8 memory layers, 2 Physics and so on... Could that be possible, then we are getting a really good overall throughput, or am I thinking wrong?

You can stack anything.

Funny how everything goes 3D these days.

Cinemas, TV sets, handheld consoles, and now even our CPUs.

Transistors just a few months ago!

Intel announced 3D transistors a few months ago (http://news.ycombinator.com/item?id=2514363).

The question I have is what would we do with processors that are 1000 times faster than now?

I remember buying my first computer and asking to upgrade to a 30mb hard-drive instead of 25mb. The sales guy said I would 'never fill 25mb'. He had no point of reference for how large graphic, files would be (this is pre-digital photography).

What new capabilities/industries will be enabled with even 1/10th of that power in a mobile device?

So... the CPU will complete its work in nanoseconds... then go back to waiting milliseconds for I/O, right?

You could make that quip about any hardware improvement.

well, except for the current bottleneck

You'll always have an IO bottleneck of some sort, even if we get memory back up to CPU speeds again.

Many, many, many, many tasks/problems are CPU bound.

RAM can be placed in the stack, eliminating slow trips accross the frontside bus. The only remaining bottleneck should be hdd access.

You can also stack flash, phase-change or memristor-based memory in there too.

Great. But the IO is still orders of magnitudes away from the processor.

Faster CPU's are important in several areas, but for 99% of problems it's RAM and stable storage that are the bottleneck.

I think the they'd want to incorporate RAM into the stack as well. (not that I think the premise is sound)

Why does HW seem to advance more than SW?

Because for most consumer-grade computing you are limited to Wintel. Multi-socket and multi-core only became popular after the 9x-NT Windows transition. 64-bits didn't became popular until Vista.

This is Mashable talking about real technology: of course they're writing bull.

I don't understand why TEC hasn't been somehow used to make 3D chips workable by now, even just for specialized applications where size and weight are not major concerns.

"Thermoelectric cooling uses the Peltier effect to create a heat flux between the junction of two different types of materials. A Peltier cooler, heater, or thermoelectric heat pump is a solid-state active heat pump which transfers heat from one side of the device to the other side against the temperature gradient (from cold to hot), with consumption of electrical energy. Such an instrument is also called a Peltier device, Peltier heat pump, solid state refrigerator, or thermoelectric cooler (TEC). The Peltier device is a heat pump: when direct current runs through it, heat is moved from one side to the other. Therefore it can be used either for heating or for cooling (refrigeration), although in practice the main application is cooling. It can also be used as a temperature controller that either heats or cools."

http://en.wikipedia.org/wiki/Thermoelectric_cooling

Peltier cooling is very inefficient; water cooling (especially with microchannels, where you could use some layers of the chip for cooling) is more efficient.

Yet we don't do that today, either. Do we? Also, water is not as easy to handle as electricity, and such a system seems to be more complex than a sandwich of computing layers and thermoelectric cooling layers. Additionally, the side where the heat finally comes out of the package, could be connected to a thermoelectric generator, thus converting some of that heat back to electricity, which could then be used to reduce the total amount of electrical input, thus raising the efficiency of the entire system.

I think I remember reading an Intel article about something like this not too long ago. You can't just do this because of a few factors. When you start stacking the die like this, the latency grows. You now have to wait for signals to travel up through multiple processor die before it gets to the die that will process the instruction. It's this reason that you end up with diminishing returns when making processors "taller".

Not only that, but unless you can increase the speed of the FSB by 100 times, you will have a serious bottleneck between the processor and the motherboard. You're now funneling 100 CPU's worth of information through a socket and medium designed for 1 CPU.

What if you go for a more SOC-like design and stick the memory in the processor tower itself? The major bottleneck there is really in talking to memory, and you could that eliminate that entirely.

> but unless you can increase the speed of the FSB by 100 times

... or stack a couple dozen gigabytes of L1 cache through a ridiculously wide internal bus. Not all chips would be processors.

Reality check: this is total bullshit.

A miracle glue will not solve power dissipation problems, not even if it were a perfect thermal conductor.

It's not a miracle, it's science. And if they can back it up, it doesn't matter if you find it inconceivable.

I didn't see any science in that video. I just saw total PR BS.

It's a sandwich. If the glue has zero thermal resistance, the silicon does not.

Science, my foot.

Nobody is asserting that it has zero thermal resistance, or that the stack will have zero thermal resistance. Only that it may have adequately low thermal resistance.

Random people on the Internet calling "bullshit" isn't how science works. Whether or not they are able to produce results is the only thing that matters.

Agree. I've seen 10+ variations of this over the last 20 years and they've all lead to dead ends, fireballs coming off wafers and 12 inch long heatsinks (HP PA-RISC for example).

The miracle solution is change the way we do things rather than rice up our existing architecture.

Maybe the singularity really is near.

Typical IBM: how make processors faster? just find a way to make them burn faster.

It's just turbo charge for processors.

Just putting a bunch of DRAM on the same chip as the CPU could make things faster and more energy-efficient by reducing the amount of time waiting for memory.

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