Game Dev Guide for Alder Lake Performance Hybrid Architecture

Intel has released an optimization guide for video game developers for the Adler Lake platform.

I think this will be interesting to any optimizing programmer out there.

Interesting notes:

1. P-cores and E-cores exist in a weird big.LITTLE architecture. The E-cores are off on their own, hanging off the ringbus.

2. E-cores share an L2 cache (!!!) in a Zen2-like cluster of 4-chips per L2 cache.

3. CPUID is going to return different results as the program shifts from P-cores to E-cores and back.

4. Bitwise operations with carry seem to have differing functionality (!!) between P-cores and E-cores? Strange... I wonder why Intel did this.

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Strange architecture. Hopefully it works out for Intel.