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So the purpose of this is basically to design an ASIC in code? I’m skeptical about “extreme silicon specialization” being the “most viable” replacement to Moore’s law. Has that not already been the case since forever? The compute intensive things has already been moved onto specialized chips ala GPUs, TPUs, etc.

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Think of this product as infrastructure-as-code for the Silicon/ASIC workflow. It's a pythonic API for the ASIC/VLSI workflow as opposed to the traditional spaghetti script TCL nightmare that holds together modern ASIC flows.

While I only really know what and FPGA is, I wonder if we're going to see a good amount of die area dedicated to an FPGA in the future, allowing software to define a new hardware accelerator for different tasks.

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