Hacker News Reader

Comment by turbinerneiter | Hacker News Reader

Do you think that fabs like TMSC or global foundries will develop tools to support IP designers with this, to drive their own business?

There is stuff like that going on in PCB design, where manufacturers make free design software, or distributors making footprint libraries.

View on HN

> There is stuff like that going on in PCB design, where manufacturers make free design software, or distributors making footprint libraries.

Totally different things. Asking TMSC how to design a RISC-V chip is akin to asking Advanced Circuits or OSH Park how to design an Intel motherboard. They can make the board for you, but they dont design it.

It's not about asking them how to design a chip, it's about them providing the tools needed to go from a Verliog design to something they can manufacture.

So I would say to that extent they do, the foundries provide dev kits with cells to use on their process, and there's definitely the same incentive, good reusable IP gets you products faster which gets them more business. I think a lot of the landscape is just driven by the sheer cost of getting it wrong. Spinning a pcb is a bummer. Needing a new mask set is so much worse.

There is eFabless, among other efforts in the vein you describe, they do a multi project wafer shuttle thing that google sponsors using skywater. It's supposedly an open source PDK, I haven't used it.

https://github.com/google/skywater-pdk

> they can make the board for you, but they dont design it.

TSMC is a manufacturer, but they still have a whole IP/Parts library that they share with their customers.

> TSMC's Design Service Alliance partners provide industry-leading, silicon-verified libraries, IP and design services directly to designers in fabless semiconductor companies, IDMs and systems houses. DSA partners provide best-of-class, silicon-verified libraries; high-performance, leading-edge intellectual property cores; unprecedented accuracy in design simulation, validation and verification; faster cycle time from specification through tapeout to finished wafers; and access to experienced designers and developers of complex functions.

https://pr.tsmc.com/english/news/2211 (year: 2000)

Reply on news.ycombinator.com