Learning about CRCs was fun for me. I had to dig into the math to figure out how to calculate the 32 bit ethernet CRC for packets being sent across a 256 bit bus for a 10 Gbps NIC I implemented on a Xilinx KC705 a few years ago. I found this guide from 1993 quite informative: https://zlib.net/crc_v3.txt
Why would there not be any CRC library for an FPGA?
The purpose of the exercise was to improve my ability to develop functionality using Verilog. Using a library would have been too easy.
What would be really clever is if it could alter, say, source code or natural language prose of sufficient length to force a specific CRC preserving the semantics of the program/prose e.g. by reordering or changing words and/or identifiers. (changing 4 bytes to arbitrary values in a comment is against the spirit of this)
Here's a repo that does something a little more generic that you can adapt for that.