But, HOW do you debug Clash?
For example, what is the design and debug flow of using Clash to target a Xilinx FPGA?
My guess is that you're going to tell me I will have to debug the generated Verilog code?
For example, what is the design and debug flow of using Clash to target a Xilinx FPGA?
My guess is that you're going to tell me I will have to debug the generated Verilog code?
One level lower, you can use Clash's signal-level simulator. Basically it gives you a synchronous stream of signal values, either as a lazy list (for "offline" simulation), or as an automaton that you can turn the crank on by feeding it the next clock cycle's inputs (for "online" simulation, i.e. where you want to do IO to compute the next input from the previous outputs). So at this level, you'd take your Pong circuit and use the automaton interface of the simulator to feed the virtual "pushbutton" states computed from e.g. keypresses, and then consume the output to do the rendering. Or simulate the whole circuit end-to-end and feed its output into a VGA interpreter, which you also get to write in Haskell.
If you need to debug at the Verilog level, you can use Clashilator (https://github.com/gergoerdi/clashilator) to automate FFI-ing into a Verilator-generated simulation.
What Clash gives you is the power and tooling of Haskell.
i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?
HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will itself place registers, rams pipeline as necessary.
That is the reason HLS doesn't reach the performance of VHDL/Verilog, these HLS tools just aren't as good as a human making the digital circuit.
Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit. Just like with VHDL or Verilog. It's just an alternative way of writing it.
>HLS generally means you compile a very high level description of computation to VHDL/Verilog.
...
>Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit.
...
>Clash is a compiler closely based on GHC that compiles Haskell code
what does it mean for clash to compile haskell code but not to come up with a digital circuit? haskell code (afaik) doesn't represent combinational or sequential logic. well maybe it does using clash (thanks to haskell crazy metaprogramming faciilities) but then what does it mean to "compile"? verilog isn't compiled, it's still synthesized to gates and luts and whatever right? what does clash compile to natively if not verilog/vhdl (which then gets synthesized)?