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Yes it is - that's what /SS is for.

Chip selects are optional. You can daily chain multiple spi devices and push the data out in a contiguous block. All the chip selects are tied together and only one cs line is used from the cpu.

> You can daily chain multiple spi devices

For some simple SPI devices, sometimes. Many SPI devices, especially more complex ones, won't let you shift data through the device without attempting to interpret it.

Or will shift out something completely different, like the response to the last command they received, just FFs so you can three wire in the general case, or even just garbage.

Flash memory devices use the CS line as an integral part of the protocol. It is definitely not optional.

If that counts then you can do exactly the same thing with a UART-based protocol, no?

Do you know of any uart hardware that'll only latch on /SS active?

No, I don't, but at the point where you're integrating a UART, adding a couple of logic gates on the data input doesn't seem too much of a stretch.

I'm not saying using UARTs instead of SPI is a good idea! I'm just saying the reason that it's not a good idea is not because UART's don't have /SS inputs.

But then how is the device supposed to know when it can respond? Most uart devices don't respect flow control. They assume they can transmit at any point.

Fair point.

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