What’s harder to find than microchips? The equipment that makes them | Hacker News Reader

What’s harder to find than microchips? The equipment that makes them

wsj.com

145 pointswallflower70 comments

Many 20+ year old fabs are still expanding and the old machines are very hard to come by. We have recently even started converting 300mm machines to run 200mm wafers because those machines are easier to find. Not every chip runs on the latest and greatest technology. For instance there is no need for a 5nm power management chip...180nm is perfectly capable of handling it efficiently.

If you look at the lists provided by IC prototyping services, you'll see that 0.7u (700nm) is still available from ON Semi:

https://europractice-ic.com/wp-content/uploads/2020/11/Gener...

...and also happens to be one of the cheapest, at 300 euros/mm^2. This was the highest-density process in the early 90s and used for CPUs such as the 486 and Pentium.

price per area isn't am especially useful metric since a smaller node gets more transistors per area for most applications.

Not only that; you can't do 5nm power management chips. At 5nm the highest voltage you can handle on your I/O is 1.2V or perhaps 1.8V. You can't even make USB transceivers on that process, which is why the Apple Silicon macs use external USB level translation chips!

Can you expand on this? Why can't 5nm chips handle higher voltages?

If your channel is very very thin, a sufficiently high voltage will cause conduction over it, even when it is not supposed to be conductive.

If you can make a "5nm" channel...why can't the machine just make the channel wider?

Like I can use a 1/8" router bit to make a 1/8" wide channel, or I can use that same router bit to make a 1" wide channel. I know these machines don't use routers but I don't really understand why they can't create larger features if they can create smaller ones.

I suspect they can.... but maybe its just not cost-effective. Why use a 5nm process to create a 180nm feature-size chip, when you can use a 180nm process for 99% less cost.

If I'm wrong please correct my misconception!

It's not width, it's depth. Things like gate oxide are deposited as a layer through a chemical process. That layer is the same thickness across the entire chip, and it scales down with the node. Gate oxide thickness determines your maximum gate voltage.

Chips aren't 2D structures, they're built out of 3D layers and all those layers have a constant thickness.

Thanks marcan :) and thanks for all your work towards bringing linux to M1.

Is there any chance such machines will be available to hobbyists some day? The only person I've ever seen attempt something like this is Sam Zeloof: https://www.youtube.com/watch?v=XrEC2LGGXn0 I'm wondering if we'll get to the point where a single person can manufacture a chip.

I wouldn't want any of that stuff at my home: https://www.bloomberg.com/news/features/2017-06-15/american-...

FYI you might like this series from Huygens optics, although his more targeted at microscale lenses than transistors.

https://youtu.be/_w0Z2Y5vaAQ

> For instance there is no need for a 5nm power management chip

But like what if you did it anyway? I remember pondering this while looking at some guitar pedal schematics. A lot of them use ICs that are basically ancient. Do newer processes have anything to offer (even if it wouldn’t be cost-efficient)?

The thing about power chips is that smaller feature size is not necessarily a good thing. With logic chips, you are essentially moving data and doing math. And you have electrons here and there representing data. It does not matter how many electrons represent a particular bit of data, as long as they can do it reliably. If you can get your feature sizes smaller and have one hundredth of the electrons represent the same bit -- good for you. As long as the data is correctly stored and the math is correct , the fewer electrons the better. Similarly it does not matter what voltage these electrons are kept at. As long as you can tell ones from zeros and can do the math correctly, the lower voltage, lower power and lower heat dissipated - the better.

It is different with power electronics. There often you have to provide a certain amount of power to actually move something, or make a motor turn, or make a speaker make sound, etc. So the amount of current and/or voltage your chips produce will actually matter.

Say you have a guitar amp. What if someone told you that at a great cost, they could make the chips at that amp a hundred times smaller. They would of course provide a hundred times less power which would make your speaker a hundred times more quiet (well, 2 db, but you get the idea). Would that be a good deal? Not really.

That is why analog and power firms like ON Semi (mentioned in the article) tend to look for old equipment. They do not need everything this small. Many of their chips actually require larger features because they have to move a lot of current and/or handle high voltages.

But that does not mean that their chips are old technology. Not all innovation is making things smaller. There is plenty of innovation going at the larger sizes.

No. Especially not for something like guitar pedals.

First, you are very likely "pad limited", the pads to connect the chip to the package are much larger than the actual active chip area.

Second, newer processes are rarely better at analog-type things. Leakage is worse, noise is worse, etc. Generally, you have to add to the transistor "length" (minimum dimension) in order to get back analog performance parameters.

Third, newer processes have to run at really small power supply voltages. Old-school metal gate CMOS in 0.5um or larger was good to 18V+--really good for things like guitar pedals.

If you have the tools, you'd be better off doing a guitar pedal in a very old technology.

First, you are very likely "pad limited", the pads to connect the chip to the package are much larger than the actual active chip area.

I remember doing the maths for this a while ago, and I believe on a 22nm process you could fit an entire 486 (1.2M transistors) in the area of a single bond pad needed for the later CPUs.

> If you have the tools, you'd be better off doing a guitar pedal in a very old technology.

The parent poster probably refers to BBD delay lines such as the MN3007 and similar devices, whose awful fidelity and noise characteristics made them famous and very recognizable in old music, especially from the 70s. Emulating them in digital is doable, but that requires more complex circuitry. If one could fit a BBD delay line and its clock generator, plus a LFO and a few low noise opamps on the same die, it would be possible to create delay based (echo/flanger/phaser/chorus etc.) pedals at extremely low costs.

For these kinds of chips there is usually nothing the new process can offer other than higher development costs, higher production costs, longer cycle times, lower yields, higher noise levels and higher EMC susceptibility.

A chip that fits its package comfortably at 180nm will not benefit from converting it 5nm process at all.

The main reasons to get with a smaller process node is to put more transistor on the same area, use less power or reduce the size of the chip, that's it. A power management chip does not qualify.

There is one more reason: if you are already invested in smaller process node or when it is difficult to find machinery for older process.

You literally can't do it. The smaller the process node, the smaller the voltage you can handle and the more delicate the chip is. At 5nm you can't even make USB transceivers; Apple M1 machines had to use external level converters for all the USB ports for this reason.

They actually can be worse in the case of space travel. You get outside the atmosphere and the sun can cause a lot of problems with newer chips.

https://www.theverge.com/tldr/2021/3/2/22309412/nasa-perseve...

Of course this isn't a problem most of us will ever deal with but I still think it's interesting.

Cost efficiency is the key, though. It'd be kind of like newer 2.5" SSDs, the actual drive takes up a fraction of the space inside. Just without the benefit of being cheaper.

Power savings would pale in comparison to cost and for many components like amps, bigger = more power.

I assume this is a non starter since no one (that I know of) is doing it, but is there a reason you can't "just" apply a 200mm mask on top of a 300mm wafer? If the limitation is the 300mm wafer costs more and makes the chips too expensive, how much would the cost have to increase in order to make it worth it? ((300mm^2pi) - (200mm^2pi))/(300mm^2*pi) % roughly?

The kind of precision and accuracy tolerances you need in these machines basically make it so that everything has to be exactly right. The 200mm mask won't have a place to "fit correctly" in the 300mm machine and so you won't be able to get the precision and accuracy you need. Remember: a silicon chip is actually made of many layers, which means many masks (1 mask per layer). Additionally, the method by which 200mm masks and 300mm masks are actually used in the etching process can vary significantly because of physics that I honestly don't have a phenomenal insight into.

Making larger wafers drives prices up, because the process of making a monocrystal larger and larger, but I don't think that's a major cost factor except for super cheap chips. The minimum cost of a 200mm wafer is about $2/in^2 and the minimum cost for a 300mm wafer is about $3/in^2, in case that's helpful.

The pad size for external wires might dominate the design for extremely simple designs, however couldn't a combination of these factors help?

* Shrink the average node size 1-2 times (E.G. 180nm to 90 or 45nm)

* Combine popular combinations of products into a single package that can have interlinks cut by laser or skipped at the metal traces stage?

* Generally consolidate similar products within fewer variations?

The slightly greater cost of the physical wafer is supposed to be offset by the increased machine throughput and the die shrinks possible, as well as ideally fewer defects by using newer processes. An extremely inexpensive set of processes for 300mm wafers would also be a good target for long term bulk semiconductor production.

Masks are not whole wafer , except in some packaging cases. The mask illuminates a 25*35 area, for both 300mm and 200mm.

Masks are not a significant expense for most processes. Nor is the bare wafer. It is all the process steps that drive the cost.

300mm qafer

I assume there's other equipment still in use on the line that can only handle 200mm wafers, otherwise it'd make sense to upgrade to 300mm and take the extra capacity increase - the masks are stepped across the wafers anyway, there's no reason in principle they can't just add more chips to fill in the extra area if they have the ability to process 300mm wafers.

I'm sure the answer is "it depends," but when do parts get so small that you stop getting higher part yield per wafer because the component just gets too small?

Are there reliability or ruggedness concerns where some use cases prefer older processes?

https://archive.md/rJ21X

Thank you :-)

Dumb question: how do chip makers predict their roadmap? If they know they’ll be able to do still finer etching in 4 years, what’s stopping them from doing it now? How can you not be able to do something today, but still know fairly accurately you’ll be able to do it in future?

Through product-management and estimation.

At scale, R&D can, to a limited extent, be commoditized. Companies/organizations (think particle-accelerators, etc.) have substantial experience bringing new technologies into production. If a new process has been proven in the lab and estimates exist for the speed with which each technology-demonstration milestone can be reached, one can credibly estimate when a new technology can reach the market. It is an inexact science, but all science is inexact.

With sufficiently accurate estimates and conservative allowances for uncertainty and schedule-slippage, one can reliably do this. Intel did so for decades, using Moore's Law as a roadmap.

Moore's Law has been sort of a special case in that it arguably functioned as sort of a self-fulfilling prophecy. "What do we need to do so that, in two years or so, we'll hit what Moore's Law would predict?"

But, as you suggest, the same general patterns apply to a lot of things. You know what you want to do. You have some idea of what you need to do to get there and how hard it's going to be. So people who have experience in such matters can make (usually) reasonable estimates of how quickly they can get there--even if they're (also usually) often optimistic. Because you're more likely to run into hiccups than unexpected breakthroughs.

> Dumb question: how do chip makers predict their roadmap?

Chipmakers don't always get it right. Past chip shortages have generally been transitory, and the punishment for overzealous buildout in response to those shortages would have been a ton of spent capex with a long recovery duration. Neither equity investors nor company executives like to lay out the kind of money needed for a new fab because it is a risk today for a reward that may or may not present itself years from today.

Chipmakers don't know the demand picture in the future, and they don't always execute the roadmap as predicted. If they did, we wouldn't have shortages today, and Intel wouldn't have delayed 10nm for so many years.

Maybe I'm not understanding your question, but it's certainly not dumb.

> If they know they’ll be able to do still finer etching in 4 years, what’s stopping them from doing it now?

They can't get the machines, for one. There's a substantial lead time for an EUV machine and ASML only keeps enough inventory to smooth out its delivery timeline. These are gigantic machines and they require much labor and expense to ship and install.

Also, remember that not every chip attempted is a chip made. As years pass, research and experience allow companies to get a higher yield out of a particular process. Higher yield means less cost per unit and more units produced per day. They won't roll out a product that is uneconomical to fab, and they won't roll out a product for which there is no chance in hell of meeting customer demand due to low yield.

> How can you not be able to do something today, but still know fairly accurately you’ll be able to do it in future?

Semiconductor hardware is one of the most high-inertia spaces in the technology sector. It's totally different from the startup world where you can build a company on little more than colorful tank-tops, ramen, and a pad of foam in your friend's dorm room. Semiconductor fabs take years to build, and the power and water infrastructure that underpins them is essential for them to function. This was the case two decades ago when Katherine Derbyshire wrote this[0] article, and it's even more the case now.

[0] https://www.dpr.com/assets/news/2002-06-01-semiconducotr-mag...

Because you can’t/don’t integrate major process changes at individual steps. You introduce entirely new or revised processes with many steps updated or new technology introduce in tandem …so called nodes.

When you move to suv, for example, you need finer etching and better cleans and many other things. Until you introduce Euclid if you don’t need the finer etch and your process “yields” well don’t fix it if it ain’t broke.

An analogy would be…star drive screws are better overall than philips screws. But I probably wouldn’t switch my car assembly line over to star drive screws by doing it one assembly station at a time.

I’d shut the line down for a weekend and change them all, or I might change them all as part of switching production over to next years model.

To create a chip requires machines from many vendors and integrating them. So there's a collaborative roadmap for the industry.

A single vendor couldn't speed this process by much, because he won't have those missing tools.

The equipment also requires folks that know the in's and out's of engineering for the equipment. This can be as much of a bottle neck as finding the equipment itself.

There are many Universities that are running old equipment for the EE departments.

And yet we're complaining about having to know git internals in order to use it :)

Why bother learning how to make hardware when you can make a better living writing software?

</s>

I don't think the /s is necessary. Many EE's go through much of the same coursework as CS students. For young EE's why would they go into the HW world when they could make so much more money working in SW. I am an EE and I am considering making the jump to SW as my daily workflow is already about 60% SW work.

At the moment at least, you could probably say the same thing about all branches of engineering. Of course, some people just prefer doing non-software things but, as you say, they'll probably end up doing quite a bit of software anyway. (Which suggests that some sort of leveling almost has to take place unless we're OK just doing without new people going into other branches of engineering and science.

Yeah I was thinking the same, no /s is necessary.

People don’t realize until it’s too late.

A good friend from high school was a top engineer for some manufacturing process, which was abandoned after a buyout. He was laid off and now runs a Dunkin franchise.

Heh I was looking at EE jobs as I have experience, but pretty much every job pays pittance totally not adequate to what you have to invest to learn this stuff.

And all the consumables that were specially manufactured for the processes used by each specific machine. Good luck finding whatever esoteric solutions you have to dump into the thing to get it to work

Since the US ban, the Chinese are hard at work at cracking the technology required for lithography. They got it until 32nm.

After they succeed and they fill their internal demands, I think we will see cheaper machines for sale.

I wouldn't wonder if in 5 years we can buy 5nm machines from Alibaba website.

The hard things start below 28nm. Before that you can get away with more traditional optics and optical litho. I fully expect there to be domestic chinese fab equipment companies competing head on with Japanese and American suppliers in processes larger than 28nm. But 5nm has taken more than a decade of R&D and is likely not easily copied.

I'd rather dream about garage scale processes with "green" less poisonous chemicals for artisanal IC production.

Has any startup attempted to solve this problem by creating new chip making hardware?

I know it takes years to even get one out the door but crazier moonshots have been funded and the ROI potential to break up a relative monopoly must be huge

Chip making is not a relatively-well documented software project with a bunch of people with knowledge available to get in the labour market

Chip making is a bunch of very very very specialized equipment, a lot of real black magic, and a few people who actually know what they're doing.

This makes it worth more to find existing, experienced manufacturers and try to get them to make more, than to reinvent a very complex wheel, with so much research involved, that the chip crises may be over, before the first devices reach production

I worked in a facility that to great fanfare built an insane building to house a $200M+ tool.

Unfortunately, it didn’t work out, and 3 years later, the tool was being hacked apart and hauled off by a caravan of scrapyard haulers.

To be honest that sounds like a tax fiddle...

It's hard to think of any enterprise that would be less suitable for a startup.

If a startup can build nuclear fission reactors or supersonic jets, it’s likely that a startup could do this too.

> If a startup can build nuclear fission reactors or supersonic jets

It still has to be proven that this can be done by a startup.

> It still has to be proven that this can be done by a startup.

I am confused. What, exactly, has to be proven? Startups have already done both things [1] [2].

(also, correction from my op: s/fission/fusion)

[1]: https://www.helionenergy.com

[2]: https://boomsupersonic.com

You can categorize fusion reactors and experimental / prototype aircraft similarly:

(1) "Our engines produce some thrust, and our wings produce some lift".

(2) "We managed to take off and land!"

(3) A working aircraft - seemingly performant, reliable, and economical enough that actual commercial airlines want to buy it.

(4) Like (3), but you've made a bunch of 'em, delivered 'em to airlines, and they're in regular real-word use...without said airlines suffering from buyer's remorse.

My understanding is that both Boom Supersonic, and everyone trying to invent a fusion reactor...are all still in category (1).

> Startups have already done both things

Startups intend to do both things. ;-)

I might be misunderstanding, but hasn't Helion already built prototype reactors, that do produce energy through fusion?

Not more energy than they put in. Just like every other fusion experiment.

Not impossible, but only if you focus on older generation chips.

Next generation chip manufacturing is insanely expensive. EUV was already a moonshot that started in 1997 and is only really usable for production in 2019. Mainly invested by its customers where only two (TSMC, Samsung) succeeded in getting it ready for production, whereas others (who already paid) are still struggling.

However, building slower chips might be more feasible. But note that in this space there are multiple competitors.

Large amounts are being thrown at this to the benifit of startups and established companies ... in China. The US sanctions have created a unique market oppurtunity for companies that can make chips outside US control.

I am way late to this thread, but I want to address a big point of confusion -- just because you have equipment capable of very fine resolution, doesn't mean you actually have to use it to produce features that small. You can keep on making 103nm gates even with equipment that can resolve 27nm features. The biggest problem with designs that have larger features is if they also specify much thicker film stacks. You can put a pretty thick layer of just about anything on a 4 inch wafer before it turns into a taco. Your ability to do that with a 12 inch wafer is pretty limited.

Also, just because you have a fab set up for a given process node, it doesn't mean that all of your photolithography equipment has the same capabilities. Some layers have more relaxed dimensions and can use less expensive optics, masks, and resists. A fab will have a mix of equipment suited to its process needs.

I wonder what I should buy in the microchip glut of 2023.

I wonder how many people it takes to enable the production of one IC. From absolute raw materials to device ready to place into a product. Machines with parts made using other machines and so on. Including the parts and processes and people's experience operating across all of it.

It would be interesting to see this whole thing mapped out. It seems to me that this might be helpful in understanding which parts of this ecosystem might be low hanging fruit.

Yes, but The Equipment That Makes Them also requires chips to function as well :)

AFAIK There are at least five members on HN working in those equipment company.

Eh, The Equipment That Makes Them could pay 1000x for those because they'll make it back right away.

One way to encourage companies to build more of these equipment is to make them open-source. This way any one who's passionate and smart can improve and lower the cost or increase the supply. The end result is more chips for all.

There is so much interest here in semiconductors. If there were a Fab start up in SV, it would be a huge hit and would bring SV back to its roots!

I think this industry essentially gatekeeped itself into slow extinction. Greedy CEOs and severly underpaid engineers is a recipe for disaster.

ASML recently sent out a memo about "low retention."

It's amazing how wasteful the whole industry is.

Now you have soldered CPUs in laptops - a great way to ensure they get replaced often ($$$ for Intel/etc) and end up in a dump in Africa somewhere, where no one will see or use the vast majority of it, ever again.

What a waste.

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