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Comment by neogodless | Hacker News Reader

It's odd, because in today's review, they have this to say:

> I have to say a side word about AVX-512 support, because we found it. If you’re prepared to disable the E-cores, and use specific motherboards, it works. After Intel spent time saying it was fused off, we dug into the story and found it still works for those that need it. It’s going to be interesting to hear how this feature will be discussed by Intel in future.

There's a whole page on it:

https://www.anandtech.com/show/17047/the-intel-12th-gen-core...

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One thing that I genuinely appreciate about AMD is that I don't need to do any research to see what CPUs support what. They have a handful of SKUs, they're all straightforward, you spend what you're willing to and go from there. I feel like Intel requires me to do a bunch of research to see if the CPU I've picked checks all the boxes.

Then I buy my AMD and deal with their weird driver issues and throw my hands up.

>I feel like Intel requires me to do a bunch of research to see if the CPU I've picked checks all the boxes.

I will not be surprised if Intel follows the AMD example soon. Pat Gelsinger is a product person. And generally Product person understand these issues better. Compared to Marketing / Financial people who have zero understanding. ( I dont want to bash them too much but seriously I have never met a marketing / financial guy who is any good at products in the 20+ years. )

Wow, and 2 FMA units/ports as well? Gotta love that the first consumer chip with 2 x AVX-512 FMA units doesn't officially support it.

This is incredibly bizarre especially given AVX-512 takes quite a lot of transistors. A late design decision to try to limit power use?

It's to allow easy e-core p-core thread migrations in the OS. They probably weren't intending the p-cores to be matched with e-cores when the RTL was being initially written for the p-cores, which would have been a few years ago.

Very good point. I guess they both cores have to have identical ISAs as they don’t know which instructions will be needed at the point at which they’re deciding which core to use.

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